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Line 8... |
Description: SDRAM Controller Core Module
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Description: SDRAM Controller Core Module
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2 types of SDRAMs are supported, 1Mx16 2 bank, or 4Mx16 4 bank.
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2 types of SDRAMs are supported, 1Mx16 2 bank, or 4Mx16 4 bank.
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This block integrate following sub modules
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This block integrate following sub modules
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sdrc_bs_convert
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sdrc_bs_convert
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convert the system side 32 bit into equvailent 16/32 SDR format
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convert the system side 32 bit into equvailent 8/16/32 SDR format
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sdrc_req_gen
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sdrc_req_gen
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This module takes requests from the app, chops them to burst booundaries
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This module takes requests from the app, chops them to burst booundaries
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if wrap=0, decodes the bank and passe the request to bank_ctl
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if wrap=0, decodes the bank and passe the request to bank_ctl
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sdrc_xfr_ctl
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sdrc_xfr_ctl
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This module takes requests from sdr_bank_ctl, runs the transfer and
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This module takes requests from sdr_bank_ctl, runs the transfer and
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Line 444... |
.twr_delay (cfg_sdr_twr_d ),
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.twr_delay (cfg_sdr_twr_d ),
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.rfsh_time (cfg_sdr_rfsh ),
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.rfsh_time (cfg_sdr_rfsh ),
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.rfsh_rmax (cfg_sdr_rfmax )
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.rfsh_rmax (cfg_sdr_rfmax )
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);
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);
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/****************************************************************************/
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// Instantiate sdr_bs_convert
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// This model handle the bus with transaltion from application layer to
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// 8/16/32 SDRAM Memory format
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// During Write Phase, this block split the data as per SDRAM Width
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// During Read Phase, This block does the re-packing based on SDRAM
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// Width
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//---------------------------------------------------------------------------
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sdrc_bs_convert #(.SDR_DW(SDR_DW) , .SDR_BW(SDR_BW)) u_bs_convert (
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sdrc_bs_convert #(.SDR_DW(SDR_DW) , .SDR_BW(SDR_BW)) u_bs_convert (
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.clk (clk ),
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.clk (clk ),
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.reset_n (reset_n ),
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.reset_n (reset_n ),
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.sdr_width (sdr_width ),
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.sdr_width (sdr_width ),
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