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[/] [sdr_ctrl/] [trunk/] [rtl/] [core/] [sdrc_define.v] - Diff between revs 51 and 54
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Rev 54 |
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`define SDR_REQ_ID_W 4
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`define SDR_REQ_ID_W 4
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`define SDR_RFSH_TIMER_W 12
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`define SDR_RFSH_TIMER_W 12
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`define SDR_RFSH_ROW_CNT_W 3
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`define SDR_RFSH_ROW_CNT_W 3
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// B2X Command
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// B2X Command
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`define OP_PRE 2'b00
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`define OP_PRE 2'b00
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`define OP_ACT 2'b01
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`define OP_ACT 2'b01
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`define OP_RD 2'b10
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`define OP_RD 2'b10
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`define OP_WR 2'b11
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`define OP_WR 2'b11
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// SDRAM Commands (CS_N, RAS_N, CAS_N, WE_N)
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// SDRAM Commands (CS_N, RAS_N, CAS_N, WE_N)
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`define SDR_DESEL 4'b1111
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`define SDR_DESEL 4'b1111
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`define SDR_NOOP 4'b0111
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`define SDR_NOOP 4'b0111
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`define SDR_ACTIVATE 4'b0011
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`define SDR_ACTIVATE 4'b0011
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`define SDR_READ 4'b0101
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`define SDR_READ 4'b0101
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`define SDR_WRITE 4'b0100
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`define SDR_WRITE 4'b0100
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`define SDR_BT 4'b0110
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`define SDR_BT 4'b0110
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`define SDR_PRECHARGE 4'b0010
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`define SDR_PRECHARGE 4'b0010
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`define SDR_REFRESH 4'b0001
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`define SDR_REFRESH 4'b0001
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`define SDR_MODE 4'b0000
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`define SDR_MODE 4'b0000
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`define ASIC 1'b1
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`define ASIC 1'b1
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`define FPGA 1'b0
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`define FPGA 1'b0
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`define TARGET_DESIGN `FPGA
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`define TARGET_DESIGN `FPGA
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// 12 bit subtractor is not feasibile for FPGA, so changed to 6 bits
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`define REQ_BW (`TARGET_DESIGN == `FPGA) ? 6 : 12 // Request Width
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