URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [rtl/] [core/] [sdrc_define.v] - Diff between revs 54 and 73

Rev 54	Rev 73
Line 23...	Line 23...
`define SDR_REFRESH 4'b0001	`define SDR_REFRESH 4'b0001
`define SDR_MODE 4'b0000	`define SDR_MODE 4'b0000

`define ASIC 1'b1	`define ASIC 1'b1
`define FPGA 1'b0	`define FPGA 1'b0
`define TARGET_DESIGN `FPGA	`// Don't Enable FPGA mode, there is functional bug in handling Active to`
	`// Precharge timing`
	`define TARGET_DESIGN `ASIC
`// 12 bit subtractor is not feasibile for FPGA, so changed to 6 bits`	`// 12 bit subtractor is not feasibile for FPGA, so changed to 6 bits`
`define REQ_BW (`TARGET_DESIGN == `FPGA) ? 6 : 12 // Request Width	`define REQ_BW (`TARGET_DESIGN == `FPGA) ? 6 : 12 // Request Width


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