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This file is part of the sdram controller project
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This file is part of the sdram controller project
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http://www.opencores.org/cores/sdr_ctrl/
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http://www.opencores.org/cores/sdr_ctrl/
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Description: SDRAM Controller Reguest Generation
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Description: SDRAM Controller Reguest Generation
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The 2Mx32 SDRAM is addressed by a 21 bit address,
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each loation is 32 bits wide.
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This 21 bit address is mapped as follows:
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ADDR [7:0] : Column Address (256 columns)
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ADDR [18:8] : Row Address (2K Rows)
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ADDR [20:19] : Bank Address (2 banks)
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The 4Mx16 SDRAM is addressed by a 22 bit address,
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Address Generation Based on cfg_colbits
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each loation is 16 bits wide.
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cfg_colbits= 2'b00
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This 22 bit address is mapped as follows:
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Address[7:0] - Column Address
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ADDR [7:0] : Column Address (256 columns)
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Address[9:8] - Bank Address
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ADDR [21:10] : Row Address (4K Rows)
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Address[21:10] - Row Address
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ADDR [21:20] : Bank Address (4 banks)
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cfg_colbits= 2'b01
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Address[8:0] - Column Address
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The 8Mx16 SDRAM is addressed by a 23 bit address,
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Address[10:9] - Bank Address
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each loation is 16 bits wide.
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Address[22:11] - Row Address
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This 23 bit address is mapped as follows:
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cfg_colbits= 2'b10
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ADDR [8:0] : Column Address (512 columns)
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Address[9:0] - Column Address
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ADDR [20:9] : Row Address (4K Rows)
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Address[11:10] - Bank Address
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ADDR [22:21] : Bank Address (4 banks)
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Address[23:12] - Row Address
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cfg_colbits= 2'b11
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Address[10:0] - Column Address
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Address[12:11] - Bank Address
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Address[24:13] - Row Address
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The SDRAMs are operated in 4 beat burst mode.
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The SDRAMs are operated in 4 beat burst mode.
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This module takes requests from the mc,
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This module takes requests from the memory controller,
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chops them to page boundaries if wrap=0,
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chops them to page boundaries if wrap=0,
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and passes the request to bank_ctl
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and passes the request to bank_ctl
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To Do:
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To Do:
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nothing
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nothing
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