| Line 24... |
Line 24... |
Address[10:0] - Column Address
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Address[10:0] - Column Address
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Address[12:11] - Bank Address
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Address[12:11] - Bank Address
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Address[24:13] - Row Address
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Address[24:13] - Row Address
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The SDRAMs are operated in 4 beat burst mode.
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The SDRAMs are operated in 4 beat burst mode.
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If Wrap = 0;
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If the current burst cross the page boundary, then this block split the request into two coressponding change in address and request length
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if the current burst cross the page boundar.
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This module takes requests from the memory controller,
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This module takes requests from the memory controller,
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chops them to page boundaries if wrap=0,
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chops them to page boundaries if wrap=0,
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and passes the request to bank_ctl
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and passes the request to bank_ctl
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To Do:
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To Do:
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| Line 71... |
Line 76... |
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/* Request from app */
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/* Request from app */
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req, // Transfer Request
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req, // Transfer Request
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req_id, // ID for this transfer
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req_id, // ID for this transfer
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req_addr, // SDRAM Address
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req_addr, // SDRAM Address
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req_addr_mask,
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req_len, // Burst Length (in 32 bit words)
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req_len, // Burst Length (in 32 bit words)
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req_wrap, // Wrap mode request (xfr_len = 4)
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req_wrap, // Wrap mode request (xfr_len = 4)
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req_wr_n, // 0 => Write request, 1 => read req
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req_wr_n, // 0 => Write request, 1 => read req
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req_ack, // Request has been accepted
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req_ack, // Request has been accepted
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sdr_core_busy_n, // SDRAM Core Busy Indication
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sdr_core_busy_n, // SDRAM Core Busy Indication
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| Line 110... |
Line 114... |
input [1:0] cfg_colbits; // 2'b00 - 8 Bit column address, 2'b01 - 9 Bit, 10 - 10 bit, 11 - 11Bits
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input [1:0] cfg_colbits; // 2'b00 - 8 Bit column address, 2'b01 - 9 Bit, 10 - 10 bit, 11 - 11Bits
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/* Request from app */
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/* Request from app */
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input req;
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input req;
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input [`SDR_REQ_ID_W-1:0] req_id;
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input [`SDR_REQ_ID_W-1:0] req_id;
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input [APP_AW:0] req_addr;
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input [APP_AW-1:0] req_addr;
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input [APP_AW-2:0] req_addr_mask;
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input [APP_RW-1:0] req_len;
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input [APP_RW-1:0] req_len;
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input req_wr_n, req_wrap;
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input req_wr_n, req_wrap;
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output req_ack, sdr_core_busy_n;
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output req_ack, sdr_core_busy_n;
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/* Req to bank_ctl */
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/* Req to bank_ctl */
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| Line 149... |
Line 152... |
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wire [1:0] r2b_ba;
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wire [1:0] r2b_ba;
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wire [11:0] r2b_raddr;
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wire [11:0] r2b_raddr;
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wire [11:0] r2b_caddr;
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wire [11:0] r2b_caddr;
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reg [APP_AW-1:0] curr_sdr_addr, sdr_addrs_mask;
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reg [APP_AW-1:0] curr_sdr_addr ;
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wire [APP_AW-1:0] next_sdr_addr, next_sdr_addr1;
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wire [APP_AW-1:0] next_sdr_addr ;
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//--------------------------------------------------------------------
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//--------------------------------------------------------------------
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// Generate the internal Adress and Burst length Based on sdram width
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// Generate the internal Adress and Burst length Based on sdram width
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//--------------------------------------------------------------------
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//--------------------------------------------------------------------
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| Line 174... |
Line 177... |
req_len_int = {req_len,2'b0};
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req_len_int = {req_len,2'b0};
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end
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end
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end
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end
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//
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//
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// The maximum length for no page overflow is 200h/100h - caddr. Split a request
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// Identify the page over flow.
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// into 2 or more requests if it crosses a page boundary.
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// Find the Maximum Burst length allowed from the selected column
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// For non-queue accesses req_addr_mask is set to all 1 and the accesses
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// address, If the requested burst length is more than the allowed Maximum
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// proceed linearly.
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// burst length, then we need to handle the bank cross over case and we
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// All queues end on a 512 byte boundary (actually a 1K boundary). For Q
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// need to split the reuest.
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// accesses req_addr_mask is set to LSB of 1 and MSB of 0 to constrain the
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// accesses within the space for a Q. When splitting and calculating the next
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// address only the LSBs are incremented, the MSBs remain = req_addr.
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//
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//
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assign max_r2b_len = (cfg_colbits == 2'b00) ? (12'h100 - r2b_caddr) :
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assign max_r2b_len = (cfg_colbits == 2'b00) ? (12'h100 - r2b_caddr) :
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(cfg_colbits == 2'b01) ? (12'h200 - r2b_caddr) :
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(cfg_colbits == 2'b01) ? (12'h200 - r2b_caddr) :
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(cfg_colbits == 2'b10) ? (12'h400 - r2b_caddr) : (12'h800 - r2b_caddr);
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(cfg_colbits == 2'b10) ? (12'h400 - r2b_caddr) : (12'h800 - r2b_caddr);
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// If the wrap = 0 and current application burst length is crossing the page boundary,
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// then request will be split into two with corresponding change in request address and request length.
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//
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// If the wrap = 0 and current burst length is not crossing the page boundary,
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// then request from application layer will be transparently passed on the bank control block.
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//
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// if the wrap = 1, then this block will not modify the request address and length.
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// The wrapping functionality will be handle by the bank control module and
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// column address will rewind back as follows XX -> FF ? 00 ? 1
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//
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assign page_ovflw = ({1'b0, lcl_req_len} > max_r2b_len) ? ~lcl_wrap : 1'b0;
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assign page_ovflw = ({1'b0, lcl_req_len} > max_r2b_len) ? ~lcl_wrap : 1'b0;
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assign r2b_len = (page_ovflw) ? max_r2b_len : lcl_req_len;
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assign r2b_len = (page_ovflw) ? max_r2b_len : lcl_req_len;
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assign next_req_len = lcl_req_len - r2b_len;
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assign next_req_len = lcl_req_len - r2b_len;
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assign next_sdr_addr1 = curr_sdr_addr + r2b_len;
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assign next_sdr_addr = curr_sdr_addr + r2b_len;
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// Wrap back based on the mask
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assign next_sdr_addr = (sdr_addrs_mask & next_sdr_addr1) |
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(~sdr_addrs_mask & curr_sdr_addr);
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assign sdr_core_busy_n = req_idle & b2r_arb_ok & sdr_init_done;
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assign sdr_core_busy_n = req_idle & b2r_arb_ok & sdr_init_done;
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assign r2b_wrap = lcl_wrap;
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assign r2b_wrap = lcl_wrap;
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| Line 224... |
Line 232... |
(req_ld) ? next_req_len : lcl_req_len;
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(req_ld) ? next_req_len : lcl_req_len;
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curr_sdr_addr <= (req_ack) ? req_addr_int :
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curr_sdr_addr <= (req_ack) ? req_addr_int :
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(req_ld) ? next_sdr_addr : curr_sdr_addr;
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(req_ld) ? next_sdr_addr : curr_sdr_addr;
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sdr_addrs_mask <= (req_ack) ?((sdr_width == 2'b00) ? req_addr_mask :
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(sdr_width == 2'b01) ? {req_addr_mask,req_addr_mask[0]} :
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{req_addr_mask,req_addr_mask[1:0]}) : sdr_addrs_mask;
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end // always @ (posedge clk)
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end // always @ (posedge clk)
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always @ (*) begin
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always @ (*) begin
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case (req_st) // synopsys full_case parallel_case
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case (req_st) // synopsys full_case parallel_case
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