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[/] [sdr_ctrl/] [trunk/] [verif/] [log/] [core_SDR_16BIT_complie.log] - Diff between revs 65 and 73

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Rev 65 Rev 73
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** Note: (vlog-1901) OptionFile "C:/cygwin/home/Dinesh/projects/sdr_ctrl/sdr_ctrl/trunk/verif/run/vlog.opt" not found. Ignored.
Model Technology ModelSim Microsemi vlog 2020.3 Compiler 2020.07 Jul 13 2020
Model Technology ModelSim ACTEL vlog 6.6d Compiler 2010.11 Nov  2 2010
Start time: 18:52:49 on Aug 27,2021
 
vlog -work work "+define+SDR_16BIT" -f filelist_core.f
-- Compiling module tb_core
-- Compiling module tb_core
-- Compiling module IS42VM16400K
-- Compiling module IS42VM16400K
-- Compiling module mt48lc2m32b2
-- Compiling module mt48lc2m32b2
-- Compiling module mt48lc8m8a2
-- Compiling module mt48lc8m8a2
-- Compiling module sdrc_core
-- Compiling module sdrc_core
Line 13... Line 14...
 
 
Top level modules:
Top level modules:
        tb_core
        tb_core
        mt48lc2m32b2
        mt48lc2m32b2
        mt48lc8m8a2
        mt48lc8m8a2
 
End time: 18:52:49 on Aug 27,2021, Elapsed time: 0:00:00
 
Errors: 0, Warnings: 0

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