| Line 20... |
Line 20... |
# Loading work.sdrc_bank_ctl
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# Loading work.sdrc_bank_ctl
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# Loading work.sdrc_bank_fsm
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# Loading work.sdrc_bank_fsm
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# Loading work.sdrc_xfr_ctl
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# Loading work.sdrc_xfr_ctl
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# Loading work.sdrc_bs_convert
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# Loading work.sdrc_bs_convert
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# Loading work.mt48lc8m8a2
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# Loading work.mt48lc8m8a2
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# ** Warning: (vsim-3017) ../tb/tb_core.sv(180): [TFMPC] - Too few port connections. Expected 44, found 43.
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# Region: /tb_core/u_dut
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# ** Warning: (vsim-3722) ../tb/tb_core.sv(180): [TFMPC] - Missing connection for port 'app_last_wr'.
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# ** Warning: (vsim-3015) ../../rtl/core/sdrc_core.v(302): [PCDPC] - Port size (31 or 31) does not match connection size (30) for port 'req_addr'. The port definition is at: ../../rtl/core/sdrc_req_gen.v(75).
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# Region: /tb_core/u_dut/u_req_gen
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# do run.do
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# do run.do
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# Write Address: 00040000, Burst Size: 4
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# Write Address: 00040000, Burst Size: 4
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# Status: Burst-No: 0 Write Address: 00040000 WriteData: 12153524
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# Status: Burst-No: 0 Write Address: 00040000 WriteData: 12153524
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# Status: Burst-No: 1 Write Address: 00040000 WriteData: c0895e81
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# Status: Burst-No: 1 Write Address: 00040000 WriteData: c0895e81
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# Status: Burst-No: 2 Write Address: 00040000 WriteData: 8484d609
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# Status: Burst-No: 2 Write Address: 00040000 WriteData: 8484d609
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| Line 2617... |
Line 2622... |
# READ STATUS: Burst-No: 38 Addr: 00162165 Rxd: 7f2767fe
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# READ STATUS: Burst-No: 38 Addr: 00162165 Rxd: 7f2767fe
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###############################
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###############################
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# STATUS: SDRAM Write/Read TEST PASSED
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# STATUS: SDRAM Write/Read TEST PASSED
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###############################
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###############################
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# ** Note: $finish : ../tb/tb_core.sv(320)
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# ** Note: $finish : ../tb/tb_core.sv(320)
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# Time: 142430 ns Iteration: 0 Instance: /tb_core
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# Time: 146610 ns Iteration: 0 Instance: /tb_core
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# Time: 146610 ns Iteration: 0 Instance: /tb_core
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# Time: 146610 ns Iteration: 0 Instance: /tb_core
|
