Line 44... |
Line 44... |
# Loading work.sdrc_bank_ctl
|
# Loading work.sdrc_bank_ctl
|
# Loading work.sdrc_bank_fsm
|
# Loading work.sdrc_bank_fsm
|
# Loading work.sdrc_xfr_ctl
|
# Loading work.sdrc_xfr_ctl
|
# Loading work.sdrc_bs_convert
|
# Loading work.sdrc_bs_convert
|
# Loading work.IS42VM16400K
|
# Loading work.IS42VM16400K
|
|
# ** Warning: (vsim-3017) ../tb/tb_core.sv(180): [TFMPC] - Too few port connections. Expected 44, found 43.
|
|
# Region: /tb_core/u_dut
|
|
# ** Warning: (vsim-3722) ../tb/tb_core.sv(180): [TFMPC] - Missing connection for port 'app_last_wr'.
|
|
# ** Warning: (vsim-3015) ../../rtl/core/sdrc_core.v(302): [PCDPC] - Port size (31 or 31) does not match connection size (30) for port 'req_addr'. The port definition is at: ../../rtl/core/sdrc_req_gen.v(75).
|
|
# Region: /tb_core/u_dut/u_req_gen
|
# do run.do
|
# do run.do
|
# Write Address: 00040000, Burst Size: 4
|
# Write Address: 00040000, Burst Size: 4
|
# Status: Burst-No: 0 Write Address: 00040000 WriteData: 12153524
|
# Status: Burst-No: 0 Write Address: 00040000 WriteData: 12153524
|
# Status: Burst-No: 1 Write Address: 00040000 WriteData: c0895e81
|
# Status: Burst-No: 1 Write Address: 00040000 WriteData: c0895e81
|
# Status: Burst-No: 2 Write Address: 00040000 WriteData: 8484d609
|
# Status: Burst-No: 2 Write Address: 00040000 WriteData: 8484d609
|
Line 2641... |
Line 2646... |
# READ STATUS: Burst-No: 38 Addr: 00162165 Rxd: 7f2767fe
|
# READ STATUS: Burst-No: 38 Addr: 00162165 Rxd: 7f2767fe
|
###############################
|
###############################
|
# STATUS: SDRAM Write/Read TEST PASSED
|
# STATUS: SDRAM Write/Read TEST PASSED
|
###############################
|
###############################
|
# ** Note: $finish : ../tb/tb_core.sv(320)
|
# ** Note: $finish : ../tb/tb_core.sv(320)
|
# Time: 91330 ns Iteration: 0 Instance: /tb_core
|
# Time: 93280 ns Iteration: 0 Instance: /tb_core
|
### test 1: basic_test1 --> PASSED
|
### test 1: basic_test1 --> PASSED
|
###########################################
|
###########################################
|
|
|
###########################################
|
###########################################
|
### Test Logs
|
### Test Logs
|