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https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk
[/] [sdr_ctrl/] [trunk/] [verif/] [tb/] [tb_core.sv] - Diff between revs 68 and 70
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| Rev 68 |
Rev 70 |
| Line 165... |
Line 165... |
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/* Parameters */
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/* Parameters */
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.sdr_init_done (sdr_init_done ),
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.sdr_init_done (sdr_init_done ),
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.cfg_req_depth (2'h3 ), //how many req. buffer should hold
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.cfg_req_depth (2'h3 ), //how many req. buffer should hold
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.cfg_sdr_en (1'b1 ),
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.cfg_sdr_en (1'b1 ),
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.cfg_sdr_mode_reg (12'h033 ),
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.cfg_sdr_mode_reg (13'h033 ),
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.cfg_sdr_tras_d (4'h4 ),
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.cfg_sdr_tras_d (4'h4 ),
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.cfg_sdr_trp_d (4'h2 ),
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.cfg_sdr_trp_d (4'h2 ),
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.cfg_sdr_trcd_d (4'h2 ),
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.cfg_sdr_trcd_d (4'h2 ),
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.cfg_sdr_cas (3'h3 ),
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.cfg_sdr_cas (3'h3 ),
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.cfg_sdr_trcar_d (4'h7 ),
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.cfg_sdr_trcar_d (4'h7 ),
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| Line 185... |
Line 185... |
assign Dq[15:8] = (sdr_den_n[1] == 1'b0) ? sdr_dout[15:8] : 8'hZZ;
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assign Dq[15:8] = (sdr_den_n[1] == 1'b0) ? sdr_dout[15:8] : 8'hZZ;
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assign Dq[23:16] = (sdr_den_n[2] == 1'b0) ? sdr_dout[23:16] : 8'hZZ;
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assign Dq[23:16] = (sdr_den_n[2] == 1'b0) ? sdr_dout[23:16] : 8'hZZ;
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assign Dq[31:24] = (sdr_den_n[3] == 1'b0) ? sdr_dout[31:24] : 8'hZZ;
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assign Dq[31:24] = (sdr_den_n[3] == 1'b0) ? sdr_dout[31:24] : 8'hZZ;
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mt48lc2m32b2 #(.data_bits(32)) u_sdram32 (
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mt48lc2m32b2 #(.data_bits(32)) u_sdram32 (
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.Dq (Dq ) ,
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.Dq (Dq ) ,
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.Addr (sdr_addr[11:0] ),
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.Addr (sdr_addr[10:0] ),
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.Ba (sdr_ba ),
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.Ba (sdr_ba ),
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.Clk (sdram_clk_d ),
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.Clk (sdram_clk_d ),
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.Cke (sdr_cke ),
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.Cke (sdr_cke ),
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.Cs_n (sdr_cs_n ),
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.Cs_n (sdr_cs_n ),
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.Ras_n (sdr_ras_n ),
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.Ras_n (sdr_ras_n ),
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