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[/] [sdr_ctrl/] [trunk/] [verif/] [tb/] [tb_core.sv] - Diff between revs 56 and 68

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Rev 56 Rev 68
Line 68... Line 68...
// Application Interface bus
// Application Interface bus
//-------------------------------------------
//-------------------------------------------
reg                   app_req            ; // Application Request
reg                   app_req            ; // Application Request
reg  [8:0]            app_req_len        ; // Burst Request length
reg  [8:0]            app_req_len        ; // Burst Request length
wire                  app_req_ack        ; // Application Request Ack
wire                  app_req_ack        ; // Application Request Ack
reg [24:0]            app_req_addr       ; // Application Address
reg [25:0]            app_req_addr       ; // Application Address
reg                   app_req_wr_n       ; // 1 -> Read, 0 -> Write
reg                   app_req_wr_n       ; // 1 -> Read, 0 -> Write
reg [dw-1:0]          app_wr_data        ; // Write Data
reg [dw-1:0]          app_wr_data        ; // Write Data
reg [dw/8-1:0]        app_wr_en_n        ; // Write Enable, Active Low
reg [dw/8-1:0]        app_wr_en_n        ; // Write Enable, Active Low
wire                  app_rd_valid       ; // Read Valid
wire                  app_rd_valid       ; // Read Valid
wire                  app_last_rd        ; // Last Read Valid
wire                  app_last_rd        ; // Last Read Valid
Line 102... Line 102...
   wire [0:0]           sdr_den_n          ; // SDRAM Data Enable
   wire [0:0]           sdr_den_n          ; // SDRAM Data Enable
   wire [0:0]           sdr_dqm            ; // SDRAM DATA Mask
   wire [0:0]           sdr_dqm            ; // SDRAM DATA Mask
`endif
`endif
 
 
wire [1:0]            sdr_ba             ; // SDRAM Bank Select
wire [1:0]            sdr_ba             ; // SDRAM Bank Select
wire [11:0]           sdr_addr           ; // SDRAM ADRESS
wire [12:0]           sdr_addr           ; // SDRAM ADRESS
wire                  sdr_init_done      ; // SDRAM Init Done
wire                  sdr_init_done      ; // SDRAM Init Done
 
 
// to fix the sdram interface timing issue
// to fix the sdram interface timing issue
wire #(2.0) sdram_clk_d = sdram_clk;
wire #(2.0) sdram_clk_d = sdram_clk;
wire #(1.0) pad_clk     = sdram_clk_d;
wire #(1.0) pad_clk     = sdram_clk_d;
Line 185... Line 185...
  assign Dq[15:8]   = (sdr_den_n[1] == 1'b0) ? sdr_dout[15:8]  : 8'hZZ;
  assign Dq[15:8]   = (sdr_den_n[1] == 1'b0) ? sdr_dout[15:8]  : 8'hZZ;
  assign Dq[23:16]  = (sdr_den_n[2] == 1'b0) ? sdr_dout[23:16] : 8'hZZ;
  assign Dq[23:16]  = (sdr_den_n[2] == 1'b0) ? sdr_dout[23:16] : 8'hZZ;
  assign Dq[31:24]  = (sdr_den_n[3] == 1'b0) ? sdr_dout[31:24] : 8'hZZ;
  assign Dq[31:24]  = (sdr_den_n[3] == 1'b0) ? sdr_dout[31:24] : 8'hZZ;
mt48lc2m32b2 #(.data_bits(32)) u_sdram32 (
mt48lc2m32b2 #(.data_bits(32)) u_sdram32 (
          .Dq                 (Dq                 ) ,
          .Dq                 (Dq                 ) ,
          .Addr               (sdr_addr           ),
          .Addr               (sdr_addr[11:0]     ),
          .Ba                 (sdr_ba             ),
          .Ba                 (sdr_ba             ),
          .Clk                (sdram_clk_d        ),
          .Clk                (sdram_clk_d        ),
          .Cke                (sdr_cke            ),
          .Cke                (sdr_cke            ),
          .Cs_n               (sdr_cs_n           ),
          .Cs_n               (sdr_cs_n           ),
          .Ras_n              (sdr_ras_n          ),
          .Ras_n              (sdr_ras_n          ),
Line 203... Line 203...
assign Dq[7:0]  = (sdr_den_n[0] == 1'b0) ? sdr_dout[7:0]  : 8'hZZ;
assign Dq[7:0]  = (sdr_den_n[0] == 1'b0) ? sdr_dout[7:0]  : 8'hZZ;
assign Dq[15:8] = (sdr_den_n[1] == 1'b0) ? sdr_dout[15:8] : 8'hZZ;
assign Dq[15:8] = (sdr_den_n[1] == 1'b0) ? sdr_dout[15:8] : 8'hZZ;
 
 
   IS42VM16400K u_sdram16 (
   IS42VM16400K u_sdram16 (
          .dq                 (Dq                 ),
          .dq                 (Dq                 ),
          .addr               (sdr_addr           ),
          .addr               (sdr_addr[11:0]     ),
          .ba                 (sdr_ba             ),
          .ba                 (sdr_ba             ),
          .clk                (sdram_clk_d        ),
          .clk                (sdram_clk_d        ),
          .cke                (sdr_cke            ),
          .cke                (sdr_cke            ),
          .csb                (sdr_cs_n           ),
          .csb                (sdr_cs_n           ),
          .rasb               (sdr_ras_n          ),
          .rasb               (sdr_ras_n          ),
Line 219... Line 219...
 
 
assign Dq[7:0]  = (sdr_den_n[0] == 1'b0) ? sdr_dout[7:0]  : 8'hZZ;
assign Dq[7:0]  = (sdr_den_n[0] == 1'b0) ? sdr_dout[7:0]  : 8'hZZ;
 
 
mt48lc8m8a2 #(.data_bits(8)) u_sdram8 (
mt48lc8m8a2 #(.data_bits(8)) u_sdram8 (
          .Dq                 (Dq                 ) ,
          .Dq                 (Dq                 ) ,
          .Addr               (sdr_addr           ),
          .Addr               (sdr_addr[11:0]     ),
          .Ba                 (sdr_ba             ),
          .Ba                 (sdr_ba             ),
          .Clk                (sdram_clk_d        ),
          .Clk                (sdram_clk_d        ),
          .Cke                (sdr_cke            ),
          .Cke                (sdr_cke            ),
          .Cs_n               (sdr_cs_n           ),
          .Cs_n               (sdr_cs_n           ),
          .Ras_n              (sdr_ras_n          ),
          .Ras_n              (sdr_ras_n          ),

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