| Line 68... |
Line 68... |
// Application Interface bus
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// Application Interface bus
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//-------------------------------------------
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//-------------------------------------------
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reg app_req ; // Application Request
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reg app_req ; // Application Request
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reg [8:0] app_req_len ; // Burst Request length
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reg [8:0] app_req_len ; // Burst Request length
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wire app_req_ack ; // Application Request Ack
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wire app_req_ack ; // Application Request Ack
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reg [24:0] app_req_addr ; // Application Address
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reg [25:0] app_req_addr ; // Application Address
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reg app_req_wr_n ; // 1 -> Read, 0 -> Write
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reg app_req_wr_n ; // 1 -> Read, 0 -> Write
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reg [dw-1:0] app_wr_data ; // Write Data
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reg [dw-1:0] app_wr_data ; // Write Data
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reg [dw/8-1:0] app_wr_en_n ; // Write Enable, Active Low
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reg [dw/8-1:0] app_wr_en_n ; // Write Enable, Active Low
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wire app_rd_valid ; // Read Valid
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wire app_rd_valid ; // Read Valid
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wire app_last_rd ; // Last Read Valid
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wire app_last_rd ; // Last Read Valid
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| Line 102... |
Line 102... |
wire [0:0] sdr_den_n ; // SDRAM Data Enable
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wire [0:0] sdr_den_n ; // SDRAM Data Enable
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wire [0:0] sdr_dqm ; // SDRAM DATA Mask
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wire [0:0] sdr_dqm ; // SDRAM DATA Mask
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`endif
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`endif
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wire [1:0] sdr_ba ; // SDRAM Bank Select
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wire [1:0] sdr_ba ; // SDRAM Bank Select
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wire [11:0] sdr_addr ; // SDRAM ADRESS
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wire [12:0] sdr_addr ; // SDRAM ADRESS
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wire sdr_init_done ; // SDRAM Init Done
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wire sdr_init_done ; // SDRAM Init Done
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// to fix the sdram interface timing issue
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// to fix the sdram interface timing issue
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wire #(2.0) sdram_clk_d = sdram_clk;
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wire #(2.0) sdram_clk_d = sdram_clk;
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wire #(1.0) pad_clk = sdram_clk_d;
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wire #(1.0) pad_clk = sdram_clk_d;
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| Line 185... |
Line 185... |
assign Dq[15:8] = (sdr_den_n[1] == 1'b0) ? sdr_dout[15:8] : 8'hZZ;
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assign Dq[15:8] = (sdr_den_n[1] == 1'b0) ? sdr_dout[15:8] : 8'hZZ;
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assign Dq[23:16] = (sdr_den_n[2] == 1'b0) ? sdr_dout[23:16] : 8'hZZ;
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assign Dq[23:16] = (sdr_den_n[2] == 1'b0) ? sdr_dout[23:16] : 8'hZZ;
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assign Dq[31:24] = (sdr_den_n[3] == 1'b0) ? sdr_dout[31:24] : 8'hZZ;
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assign Dq[31:24] = (sdr_den_n[3] == 1'b0) ? sdr_dout[31:24] : 8'hZZ;
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mt48lc2m32b2 #(.data_bits(32)) u_sdram32 (
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mt48lc2m32b2 #(.data_bits(32)) u_sdram32 (
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.Dq (Dq ) ,
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.Dq (Dq ) ,
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.Addr (sdr_addr ),
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.Addr (sdr_addr[11:0] ),
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.Ba (sdr_ba ),
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.Ba (sdr_ba ),
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.Clk (sdram_clk_d ),
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.Clk (sdram_clk_d ),
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.Cke (sdr_cke ),
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.Cke (sdr_cke ),
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.Cs_n (sdr_cs_n ),
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.Cs_n (sdr_cs_n ),
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.Ras_n (sdr_ras_n ),
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.Ras_n (sdr_ras_n ),
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| Line 203... |
Line 203... |
assign Dq[7:0] = (sdr_den_n[0] == 1'b0) ? sdr_dout[7:0] : 8'hZZ;
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assign Dq[7:0] = (sdr_den_n[0] == 1'b0) ? sdr_dout[7:0] : 8'hZZ;
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assign Dq[15:8] = (sdr_den_n[1] == 1'b0) ? sdr_dout[15:8] : 8'hZZ;
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assign Dq[15:8] = (sdr_den_n[1] == 1'b0) ? sdr_dout[15:8] : 8'hZZ;
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IS42VM16400K u_sdram16 (
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IS42VM16400K u_sdram16 (
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.dq (Dq ),
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.dq (Dq ),
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.addr (sdr_addr ),
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.addr (sdr_addr[11:0] ),
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.ba (sdr_ba ),
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.ba (sdr_ba ),
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.clk (sdram_clk_d ),
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.clk (sdram_clk_d ),
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.cke (sdr_cke ),
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.cke (sdr_cke ),
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.csb (sdr_cs_n ),
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.csb (sdr_cs_n ),
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.rasb (sdr_ras_n ),
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.rasb (sdr_ras_n ),
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| Line 219... |
Line 219... |
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assign Dq[7:0] = (sdr_den_n[0] == 1'b0) ? sdr_dout[7:0] : 8'hZZ;
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assign Dq[7:0] = (sdr_den_n[0] == 1'b0) ? sdr_dout[7:0] : 8'hZZ;
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mt48lc8m8a2 #(.data_bits(8)) u_sdram8 (
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mt48lc8m8a2 #(.data_bits(8)) u_sdram8 (
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.Dq (Dq ) ,
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.Dq (Dq ) ,
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.Addr (sdr_addr ),
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.Addr (sdr_addr[11:0] ),
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.Ba (sdr_ba ),
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.Ba (sdr_ba ),
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.Clk (sdram_clk_d ),
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.Clk (sdram_clk_d ),
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.Cke (sdr_cke ),
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.Cke (sdr_cke ),
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.Cs_n (sdr_cs_n ),
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.Cs_n (sdr_cs_n ),
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.Ras_n (sdr_ras_n ),
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.Ras_n (sdr_ras_n ),
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