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[/] [sdr_ctrl/] [trunk/] [verif/] [tb/] [tb_top.sv] - Diff between revs 25 and 30

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Rev 25 Rev 30
Line 45... Line 45... 
 
 
 
 
// This testbench verify with SDRAM TOP
 
// This testbench verify with SDRAM TOP
 
 
 
 
 
module tb_top;
 
module tb_top;
 
 
 
 
 
parameter P_SYS  = 10;     //    100MHz
 
parameter P_SYS  = 10;     //    200MHz
 
 
 
parameter P_SDR  = 20;     //    100MHz
 
 
 
 
 
// General
 
// General
 
reg            RESETN;
 
reg            RESETN;
 
reg            sdram_clk;
 
reg            sdram_clk;
 
 
 
reg            sys_clk;
 
 
 
 
 
 
 
initial sys_clk = 0;
 
initial sdram_clk = 0;
 
initial sdram_clk = 0;
 
 
 
 
 
always #(P_SYS/2) sdram_clk = !sdram_clk;
 
always #(P_SYS/2) sys_clk = !sys_clk;
 
 
 
always #(P_SDR/2) sdram_clk = !sdram_clk;
 
 
 
 
 
parameter      dw              = 32;  // data width
 
parameter      dw              = 32;  // data width
 
parameter      tw              = 8;   // tag id width
 
parameter      tw              = 8;   // tag id width
 
parameter      bl              = 5;   // burst_lenght_width
 
parameter      bl              = 5;   // burst_lenght_width
 
 
 
 
 
//-------------------------------------------
 
//-------------------------------------------
 
// Application Interface bus
 
// WISH BONE Interface
 
//-------------------------------------------
 
//-------------------------------------------
 
reg                   app_req            ; // Application Request
 
//--------------------------------------
 
reg  [8:0]            app_req_len        ; // Burst Request length
 
// Wish Bone Interface
 
wire                  app_req_ack        ; // Application Request Ack
 
// -------------------------------------
 
reg [29:0]            app_req_addr       ; // Application Address
 
reg             wb_stb_i           ;
 
reg                   app_req_wr_n       ; // 1 -> Read, 0 -> Write
 
wire            wb_ack_o           ;
 
reg [dw-1:0]          app_wr_data        ; // Write Data
 
reg  [29:0]     wb_addr_i          ;
 
reg [dw/8-1:0]        app_wr_en_n        ; // Write Enable, Active Low
 
reg             wb_we_i            ; // 1 - Write, 0 - Read
 
wire                  app_rd_valid       ; // Read Valid
 
reg  [dw-1:0]   wb_dat_i           ;
 
wire [dw-1:0]         app_rd_data        ; // Read Data
 
reg  [dw/8-1:0] wb_sel_i           ; // Byte enable
 
 
 
wire  [dw-1:0]  wb_dat_o           ;
 
 
 
reg             wb_cyc_i           ;
 
 
 
reg   [2:0]     wb_cti_i           ;
 
 
 
 
 
 
 
 
 
 
 
 
 
//--------------------------------------------
 
//--------------------------------------------
 
// SDRAM I/F
 
// SDRAM I/F
 
//--------------------------------------------
 
//--------------------------------------------
 
 
 
 
Line 102... Line 111... 
wire [11:0]           sdr_addr           ; // SDRAM ADRESS
 
wire [11:0]           sdr_addr           ; // SDRAM ADRESS
 
wire                  sdr_init_done      ; // SDRAM Init Done
 
wire                  sdr_init_done      ; // SDRAM Init Done
 
 
 
 
 
// to fix the sdram interface timing issue
 
// to fix the sdram interface timing issue
 
wire #(2.0) sdram_clk_d = sdram_clk;
 
wire #(2.0) sdram_clk_d = sdram_clk;
 
wire #(1.0) pad_clk     = sdram_clk_d;
 
wire #(1.0) sdram_pad_clk = sdram_clk_d;
 
 
 
 
 
`ifdef SDR_32BIT
 
`ifdef SDR_32BIT
 
 
 
 
 
   sdrc_core #(.SDR_DW(32),.SDR_BW(4)) u_dut(
 
   sdrc_top #(.SDR_DW(32),.SDR_BW(4)) u_dut(
 
`elsif SDR_16BIT
 
`elsif SDR_16BIT
 
   sdrc_core #(.SDR_DW(16),.SDR_BW(2)) u_dut(
 
   sdrc_top #(.SDR_DW(16),.SDR_BW(2)) u_dut(
 
`else  // 8 BIT SDRAM
 
`else  // 8 BIT SDRAM
 
   sdrc_core #(.SDR_DW(8),.SDR_BW(1)) u_dut(
 
   sdrc_top #(.SDR_DW(8),.SDR_BW(1)) u_dut(
 
`endif
 
`endif
 
      // System
 
      // System
 
          .clk                (sdram_clk          ),
 
 
 
          .reset_n            (RESETN             ),
 
 
 
          .pad_clk            (pad_clk            ),
 
 
 
`ifdef SDR_32BIT
 
`ifdef SDR_32BIT
 
          .sdr_width          (2'b00              ), // 32 BIT SDRAM
 
          .sdr_width          (2'b00              ), // 32 BIT SDRAM
 
`elsif SDR_16BIT
 
`elsif SDR_16BIT
 
          .sdr_width          (2'b01              ), // 16 BIT SDRAM
 
          .sdr_width          (2'b01              ), // 16 BIT SDRAM
 
`else
 
`else
 
          .sdr_width          (2'b10              ), // 8 BIT SDRAM
 
          .sdr_width          (2'b10              ), // 8 BIT SDRAM
 
`endif
 
`endif
 
          .cfg_colbits        (2'b00              ), // 8 Bit Column Address
 
          .cfg_colbits        (2'b00              ), // 8 Bit Column Address
 
 
 
 
 
 
 
/* WISH BONE */
 
/* Request from app */
 
          .wb_rst_i           (!RESETN            ),
 
          .app_req            (app_req            ),    // Transfer Request
 
          .wb_clk_i           (sys_clk            ),
 
          .app_req_addr       (app_req_addr       ),    // SDRAM Address
 
 
 
          .app_req_addr_mask  (29'h1FFF_FFFF      ),    // Address mask for queue wrap
 
          .wb_stb_i           (wb_stb_i           ),
 
          .app_req_len        (app_req_len        ),    // Burst Length (in 16 bit words)
 
          .wb_ack_o           (wb_ack_o           ),
 
          .app_req_wrap       (1'b0               ),    // Wrap mode request (xfr_len = 4)
 
          .wb_addr_i          (wb_addr_i          ),
 
          .app_req_wr_n       (app_req_wr_n       ),    // 0 => Write request, 1 => read req
 
          .wb_we_i            (wb_we_i            ),
 
          .app_req_ack        (app_req_ack        ),    // Request has been accepted
 
          .wb_dat_i           (wb_dat_i           ),
 
          .sdr_core_busy_n    (                   ),    // OK to arbitrate next request
 
          .wb_sel_i           (wb_sel_i           ),
 
 
 
          .wb_dat_o           (wb_dat_o           ),
 
          .app_wr_data        (app_wr_data        ),
 
          .wb_cyc_i           (wb_cyc_i           ),
 
          .app_wr_en_n        (app_wr_en_n        ),
 
          .wb_cti_i           (wb_cti_i           ),
 
          .app_rd_data        (app_rd_data        ),
 
 
 
          .app_rd_valid       (app_rd_valid       ),
 
 
 
          .app_wr_next_req    (app_wr_next_req    ),
 
 
 
          .app_req_dma_last   (app_req            ),
 
 
 
 
 
 
 
/* Interface to SDRAMs */
 
/* Interface to SDRAMs */
 
 
 
          .sdram_clk          (sdram_clk          ),
 
 
 
          .sdram_pad_clk      (sdram_pad_clk      ),
 
 
 
          .sdram_resetn       (RESETN             ),
 
          .sdr_cs_n           (sdr_cs_n           ),
 
          .sdr_cs_n           (sdr_cs_n           ),
 
          .sdr_cke            (sdr_cke            ),
 
          .sdr_cke            (sdr_cke            ),
 
          .sdr_ras_n          (sdr_ras_n          ),
 
          .sdr_ras_n          (sdr_ras_n          ),
 
          .sdr_cas_n          (sdr_cas_n          ),
 
          .sdr_cas_n          (sdr_cas_n          ),
 
          .sdr_we_n           (sdr_we_n           ),
 
          .sdr_we_n           (sdr_we_n           ),
Line 242... Line 247... 
// Test Case
 
// Test Case
 
/////////////////////////////////////////////////////////////////////////
 
/////////////////////////////////////////////////////////////////////////
 
 
 
 
 
initial begin //{
 
initial begin //{
 
  ErrCnt          = 0;
 
  ErrCnt          = 0;
 
   app_req_addr  = 0;
 
   wb_addr_i      = 0;
 
   app_wr_data    = 0;
 
   wb_dat_i      = 0;
 
   app_wr_en_n    = 4'hF;
 
   wb_sel_i       = 4'h0;
 
   app_req_wr_n   = 0;
 
   wb_we_i        = 0;
 
   app_req        = 0;
 
   wb_stb_i       = 0;
 
   app_req_len    = 0;
 
   wb_cyc_i       = 0;
 
 
 
 
 
  RESETN    = 1'h1;
 
  RESETN    = 1'h1;
 
 
 
 
 
 #100
 
 #100
 
  // Applying reset
 
  // Applying reset
Line 301... Line 306... 
 
 
 
 
task burst_write;
 
task burst_write;
 
input [31:0] Address;
 
input [31:0] Address;
 
int i;
 
int i;
 
begin
 
begin
 
   @ (negedge sdram_clk);
 
   @ (negedge sys_clk);
 
   app_req        = 1;
 
 
 
   app_wr_en_n    = 0;
 
 
 
   app_req_wr_n   = 1'b0;
 
 
 
   $display("Write Address: %x, Burst Size: %d",Address,wrdfifo.size);
 
   $display("Write Address: %x, Burst Size: %d",Address,wrdfifo.size);
 
   app_req_addr  = Address[31:2];
 
 
 
   app_req_len    = wrdfifo.size;
 
 
 
 
 
 
 
   // wait for app_req_ack == 1
 
 
 
   do begin
 
 
 
       @ (posedge sdram_clk);
 
 
 
   end while(app_req_ack == 1'b0);
 
 
 
   @ (negedge sdram_clk);
 
 
 
   app_req           = 0;
 
 
 
 
 
 
 
   for(i=0; i < wrdfifo.size; i++) begin
 
   for(i=0; i < wrdfifo.size; i++) begin
 
      app_wr_data     = wrdfifo[i];
 
      wb_stb_i        = 1;
 
 
 
      wb_cyc_i        = 1;
 
 
 
      wb_we_i         = 1;
 
 
 
      wb_sel_i        = 4'b1111;
 
 
 
      wb_addr_i       = Address[31:2]+i;
 
 
 
      wb_dat_i        = wrdfifo[i];
 
 
 
 
 
      do begin
 
      do begin
 
          @ (posedge sdram_clk);
 
          @ (posedge sys_clk);
 
      end while(app_wr_next_req == 1'b0);
 
      end while(wb_ack_o == 1'b0);
 
          @ (negedge sdram_clk);
 
          @ (negedge sys_clk);
 
 
 
 
 
       $display("Status: Burst-No: %d  Write Address: %x  WriteData: %x ",i,Address,app_wr_data);
 
       $display("Status: Burst-No: %d  Write Address: %x  WriteData: %x ",i,wb_addr_i,wb_dat_i);
 
   end
 
   end
 
   app_req           = 0;
 
   wb_stb_i           = 0;
 
   app_wr_en_n       = 4'hF;
 
   wb_cyc_i           = 0;
 
end
 
end
 
endtask
 
endtask
 
 
 
 
 
task burst_read;
 
task burst_read;
 
input [31:0] Address;
 
input [31:0] Address;
 
 
 
 
 
int i,j;
 
int i,j;
 
reg [31:0]   rd_data;
 
reg [31:0]   rd_data;
 
begin
 
begin
 
   @ (negedge sdram_clk);
 
   @ (negedge sys_clk);
 
 
 
 
 
      app_req        = 1;
 
 
 
      app_wr_en_n    = 0;
 
 
 
      app_req_wr_n   = 1;
 
 
 
      app_req_addr   = Address[29:2];
 
 
 
      app_req_len    = wrdfifo.size;
 
 
 
      // wait for app_req_ack == 1
 
 
 
      do begin
 
 
 
          @ (posedge sdram_clk);
 
 
 
      end while(app_req_ack == 1'b0);
 
 
 
      @ (negedge sdram_clk);
 
 
 
      app_req           = 0;
 
 
 
 
 
 
 
      for(j=0; j < wrdfifo.size; j++) begin
 
      for(j=0; j < wrdfifo.size; j++) begin
 
         wait(app_rd_valid == 1);
 
         wb_stb_i        = 1;
 
         if(app_rd_data !== wrdfifo[j]) begin
 
         wb_cyc_i        = 1;
 
             $display("READ ERROR: Burst-No: %d Addr: %x Rxp: %x Exd: %x",j,Address+(j*2),app_rd_data,wrdfifo[j]);
 
         wb_we_i         = 0;
 
 
 
         wb_addr_i       = Address[31:2]+j;
 
 
 
 
 
 
 
         do begin
 
 
 
             @ (posedge sys_clk);
 
 
 
         end while(wb_ack_o == 1'b0);
 
 
 
         if(wb_dat_o !== wrdfifo[j]) begin
 
 
 
             $display("READ ERROR: Burst-No: %d Addr: %x Rxp: %x Exd: %x",j,wb_addr_i,wb_dat_o,wrdfifo[j]);
 
             ErrCnt = ErrCnt+1;
 
             ErrCnt = ErrCnt+1;
 
         end else begin
 
         end else begin
 
             $display("READ STATUS: Burst-No: %d Addr: %x Rxd: %x",j,Address+(j*2),app_rd_data);
 
             $display("READ STATUS: Burst-No: %d Addr: %x Rxd: %x",j,wb_addr_i,wb_dat_o);
 
         end
 
         end
 
         @ (posedge sdram_clk);
 
 
 
         @ (negedge sdram_clk);
 
         @ (negedge sdram_clk);
 
      end
 
      end
 
 
 
   wb_stb_i           = 0;
 
 
 
   wb_cyc_i           = 0;
 
end
 
end
 
endtask
 
endtask
 
 
 
 
 
 
 
 
 
endmodule
 
endmodule

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