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[/] [sdr_ctrl/] [trunk/] [verif/] [tb/] [tb_top.sv] - Diff between revs 53 and 56

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Rev 53 Rev 56
Line 76... Line 76...
//--------------------------------------
//--------------------------------------
// Wish Bone Interface
// Wish Bone Interface
// -------------------------------------
// -------------------------------------
reg             wb_stb_i           ;
reg             wb_stb_i           ;
wire            wb_ack_o           ;
wire            wb_ack_o           ;
reg  [29:0]     wb_addr_i          ;
reg  [24:0]     wb_addr_i          ;
reg             wb_we_i            ; // 1 - Write, 0 - Read
reg             wb_we_i            ; // 1 - Write, 0 - Read
reg  [dw-1:0]   wb_dat_i           ;
reg  [dw-1:0]   wb_dat_i           ;
reg  [dw/8-1:0] wb_sel_i           ; // Byte enable
reg  [dw/8-1:0] wb_sel_i           ; // Byte enable
wire  [dw-1:0]  wb_dat_o           ;
wire  [dw-1:0]  wb_dat_o           ;
reg             wb_cyc_i           ;
reg             wb_cyc_i           ;
Line 450... Line 450...
 
 
       $display("Status: Burst-No: %d  Write Address: %x  WriteData: %x ",i,wb_addr_i,wb_dat_i);
       $display("Status: Burst-No: %d  Write Address: %x  WriteData: %x ",i,wb_addr_i,wb_dat_i);
   end
   end
   wb_stb_i           = 0;
   wb_stb_i           = 0;
   wb_cyc_i           = 0;
   wb_cyc_i           = 0;
 
   wb_we_i         = 'hx;
 
   wb_sel_i        = 'hx;
 
   wb_addr_i       = 'hx;
 
   wb_dat_i        = 'hx;
end
end
endtask
endtask
 
 
task burst_read;
task burst_read;
reg [31:0] Address;
reg [31:0] Address;
Line 485... Line 489...
         end
         end
         @ (negedge sdram_clk);
         @ (negedge sdram_clk);
      end
      end
   wb_stb_i           = 0;
   wb_stb_i           = 0;
   wb_cyc_i           = 0;
   wb_cyc_i           = 0;
 
   wb_we_i         = 'hx;
 
   wb_addr_i       = 'hx;
end
end
endtask
endtask
 
 
 
 
endmodule
endmodule

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