URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [verif/] [tb/] [tb_top.sv] - Diff between revs 68 and 70

Rev 68	Rev 70
Line 157...	Line 157...

`/* Parameters */`	`/* Parameters */`
`.sdr_init_done (sdr_init_done ),`	`.sdr_init_done (sdr_init_done ),`
`.cfg_req_depth (2'h3 ), //how many req. buffer should hold`	`.cfg_req_depth (2'h3 ), //how many req. buffer should hold`
`.cfg_sdr_en (1'b1 ),`	`.cfg_sdr_en (1'b1 ),`
`.cfg_sdr_mode_reg (12'h033 ),`	`.cfg_sdr_mode_reg (13'h033 ),`
`.cfg_sdr_tras_d (4'h4 ),`	`.cfg_sdr_tras_d (4'h4 ),`
`.cfg_sdr_trp_d (4'h2 ),`	`.cfg_sdr_trp_d (4'h2 ),`
`.cfg_sdr_trcd_d (4'h2 ),`	`.cfg_sdr_trcd_d (4'h2 ),`
`.cfg_sdr_cas (3'h3 ),`	`.cfg_sdr_cas (3'h3 ),`
`.cfg_sdr_trcar_d (4'h7 ),`	`.cfg_sdr_trcar_d (4'h7 ),`
Line 173...	Line 173...


`ifdef SDR_32BIT	`ifdef SDR_32BIT
`mt48lc2m32b2 #(.data_bits(32)) u_sdram32 (`	`mt48lc2m32b2 #(.data_bits(32)) u_sdram32 (`
`.Dq (Dq ) ,`	`.Dq (Dq ) ,`
`.Addr (sdr_addr[11:0] ),`	`.Addr (sdr_addr[10:0] ),`
`.Ba (sdr_ba ),`	`.Ba (sdr_ba ),`
`.Clk (sdram_clk_d ),`	`.Clk (sdram_clk_d ),`
`.Cke (sdr_cke ),`	`.Cke (sdr_cke ),`
`.Cs_n (sdr_cs_n ),`	`.Cs_n (sdr_cs_n ),`
`.Ras_n (sdr_ras_n ),`	`.Ras_n (sdr_ras_n ),`