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type mem_type is array(natural range <>) of std_logic_vector(31 downto 0);
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type mem_type is array(natural range <>) of std_logic_vector(31 downto 0);
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signal mem: mem_type(0 to (2**(abits-2)-1));
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signal mem: mem_type(0 to (2**(abits-2)-1));
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signal s_load: std_ulogic := '1';
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signal s_load: std_ulogic := '1';
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signal s_rdata: std_logic_vector(31 downto 0) := (others => '0');
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signal s_rdata: std_logic_vector(31 downto 0) := (others => '0');
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signal s_wdata: std_logic_vector(31 downto 0) := (others => '0');
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signal s_ready: std_ulogic := '0';
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signal s_ready: std_ulogic := '0';
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signal s_write: std_ulogic := '0';
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signal s_write: std_ulogic := '0';
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signal s_waddr: std_logic_vector(31 downto 0) := (others => '0');
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signal s_waddr: std_logic_vector(31 downto 0) := (others => '0');
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signal s_wsize: std_logic_vector(2 downto 0) := "000";
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signal s_wsize: std_logic_vector(2 downto 0) := "000";
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Line 86... |
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begin
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begin
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ahbo.hready <= s_ready;
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ahbo.hready <= s_ready;
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ahbo.hresp <= HRESP_OKAY;
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ahbo.hresp <= HRESP_OKAY;
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ahbo.hrdata <= s_rdata;
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ahbo.hrdata <= ahbdrivedata(s_rdata);
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ahbo.hsplit <= (others => '0');
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ahbo.hsplit <= (others => '0');
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ahbo.hcache <= '1';
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ahbo.hirq <= (others => '0');
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ahbo.hirq <= (others => '0');
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ahbo.hconfig <= hconfig;
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ahbo.hconfig <= hconfig;
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ahbo.hindex <= hindex;
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ahbo.hindex <= hindex;
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s_wdata <= ahbreadword(ahbi.hwdata, s_waddr(4 downto 2));
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process (clk) is
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process (clk) is
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procedure loadfile is
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procedure loadfile is
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file fd: text open read_mode is fname;
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file fd: text open read_mode is fname;
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variable lin: line;
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variable lin: line;
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if s_write = '1' and s_ready = '1' then
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if s_write = '1' and s_ready = '1' then
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case s_wsize is
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case s_wsize is
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when HSIZE_BYTE =>
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when HSIZE_BYTE =>
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case s_waddr(1 downto 0) is
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case s_waddr(1 downto 0) is
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when "00" =>
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when "00" =>
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mem(wa)(31 downto 24) <= ahbi.hwdata(31 downto 24);
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mem(wa)(31 downto 24) <= s_wdata(31 downto 24);
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when "01" =>
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when "01" =>
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mem(wa)(23 downto 16) <= ahbi.hwdata(23 downto 16);
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mem(wa)(23 downto 16) <= s_wdata(23 downto 16);
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when "10" =>
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when "10" =>
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mem(wa)(15 downto 8) <= ahbi.hwdata(15 downto 8);
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mem(wa)(15 downto 8) <= s_wdata(15 downto 8);
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when others =>
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when others =>
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mem(wa)(7 downto 0) <= ahbi.hwdata(7 downto 0);
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mem(wa)(7 downto 0) <= s_wdata(7 downto 0);
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end case;
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end case;
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when HSIZE_HWORD =>
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when HSIZE_HWORD =>
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if s_waddr(1) = '1' then
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if s_waddr(1) = '1' then
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mem(wa)(15 downto 0) <= ahbi.hwdata(15 downto 0);
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mem(wa)(15 downto 0) <= s_wdata(15 downto 0);
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else
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else
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mem(wa)(31 downto 16) <= ahbi.hwdata(31 downto 16);
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mem(wa)(31 downto 16) <= s_wdata(31 downto 16);
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end if;
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end if;
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when others =>
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when others =>
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mem(wa) <= ahbi.hwdata;
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mem(wa) <= s_wdata;
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end case;
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end case;
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end if;
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end if;
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if rstn = '0' then
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if rstn = '0' then
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s_ready <= '0';
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s_ready <= '0';
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