--
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--
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-- AHB slave simulating random access memory.
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-- AHB slave simulating random access memory.
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-- Initial contents are loaded from an SREC file at the start of the simulation.
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-- Initial contents are loaded from an SREC file at the start of the simulation.
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--
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--
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all, ieee.numeric_std.all;
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use ieee.std_logic_1164.all, ieee.numeric_std.all;
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use std.textio.all;
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use std.textio.all;
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library grlib;
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library grlib;
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use grlib.amba.all;
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use grlib.amba.all;
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use grlib.devices.all;
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use grlib.devices.all;
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use grlib.stdlib.all;
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use grlib.stdlib.all;
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entity ahbram_loadfile is
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entity ahbram_loadfile is
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generic (
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generic (
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hindex: integer;
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hindex: integer;
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haddr: integer;
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haddr: integer;
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hmask: integer := 16#fff#;
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hmask: integer := 16#fff#;
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abits: integer range 10 to 24;
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abits: integer range 10 to 24;
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fname: string );
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fname: string );
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port (
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port (
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rstn: in std_logic;
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rstn: in std_logic;
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clk: in std_logic;
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clk: in std_logic;
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ahbi: in ahb_slv_in_type;
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ahbi: in ahb_slv_in_type;
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ahbo: out ahb_slv_out_type );
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ahbo: out ahb_slv_out_type );
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end entity ahbram_loadfile;
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end entity ahbram_loadfile;
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architecture ahbram_arch of ahbram_loadfile is
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architecture ahbram_arch of ahbram_loadfile is
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type mem_type is array(natural range <>) of std_logic_vector(31 downto 0);
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type mem_type is array(natural range <>) of std_logic_vector(31 downto 0);
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signal mem: mem_type(0 to (2**(abits-2)-1));
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signal mem: mem_type(0 to (2**(abits-2)-1));
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signal s_load: std_ulogic := '1';
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signal s_load: std_ulogic := '1';
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signal s_rdata: std_logic_vector(31 downto 0) := (others => '0');
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signal s_rdata: std_logic_vector(31 downto 0) := (others => '0');
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signal s_wdata: std_logic_vector(31 downto 0) := (others => '0');
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signal s_ready: std_ulogic := '0';
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signal s_ready: std_ulogic := '0';
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signal s_write: std_ulogic := '0';
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signal s_write: std_ulogic := '0';
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signal s_waddr: std_logic_vector(31 downto 0) := (others => '0');
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signal s_waddr: std_logic_vector(31 downto 0) := (others => '0');
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signal s_wsize: std_logic_vector(2 downto 0) := "000";
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signal s_wsize: std_logic_vector(2 downto 0) := "000";
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constant hconfig : ahb_config_type := (
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constant hconfig : ahb_config_type := (
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0 => ahb_device_reg(VENDOR_GAISLER, GAISLER_AHBRAM, 0, 0, 0),
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0 => ahb_device_reg(VENDOR_GAISLER, GAISLER_AHBRAM, 0, 0, 0),
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4 => ahb_membar(haddr, '1', '1', hmask),
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4 => ahb_membar(haddr, '1', '1', hmask),
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others => zero32);
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others => zero32);
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function fromhex(s: string) return unsigned is
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function fromhex(s: string) return unsigned is
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variable v: unsigned(31 downto 0);
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variable v: unsigned(31 downto 0);
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variable t: unsigned(3 downto 0);
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variable t: unsigned(3 downto 0);
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begin
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begin
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v := to_unsigned(0, 32);
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v := to_unsigned(0, 32);
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for i in s'range loop
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for i in s'range loop
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case s(i) is
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case s(i) is
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when '0' => t := "0000";
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when '0' => t := "0000";
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when '1' => t := "0001";
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when '1' => t := "0001";
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when '2' => t := "0010";
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when '2' => t := "0010";
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when '3' => t := "0011";
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when '3' => t := "0011";
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when '4' => t := "0100";
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when '4' => t := "0100";
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when '5' => t := "0101";
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when '5' => t := "0101";
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when '6' => t := "0110";
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when '6' => t := "0110";
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when '7' => t := "0111";
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when '7' => t := "0111";
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when '8' => t := "1000";
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when '8' => t := "1000";
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when '9' => t := "1001";
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when '9' => t := "1001";
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when 'a' => t := "1010";
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when 'a' => t := "1010";
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when 'A' => t := "1010";
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when 'A' => t := "1010";
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when 'b' => t := "1011";
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when 'b' => t := "1011";
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when 'B' => t := "1011";
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when 'B' => t := "1011";
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when 'c' => t := "1100";
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when 'c' => t := "1100";
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when 'C' => t := "1100";
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when 'C' => t := "1100";
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when 'd' => t := "1101";
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when 'd' => t := "1101";
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when 'D' => t := "1101";
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when 'D' => t := "1101";
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when 'e' => t := "1110";
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when 'e' => t := "1110";
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when 'E' => t := "1110";
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when 'E' => t := "1110";
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when 'f' => t := "1111";
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when 'f' => t := "1111";
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when 'F' => t := "1111";
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when 'F' => t := "1111";
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when others => assert false report "invalid syntax in SREC file";
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when others => assert false report "invalid syntax in SREC file";
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end case;
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end case;
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v := v(27 downto 0) & t;
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v := v(27 downto 0) & t;
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end loop;
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end loop;
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return v;
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return v;
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end function;
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end function;
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begin
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begin
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ahbo.hready <= s_ready;
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ahbo.hready <= s_ready;
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ahbo.hresp <= HRESP_OKAY;
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ahbo.hresp <= HRESP_OKAY;
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ahbo.hrdata <= s_rdata;
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ahbo.hrdata <= ahbdrivedata(s_rdata);
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ahbo.hsplit <= (others => '0');
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ahbo.hsplit <= (others => '0');
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ahbo.hcache <= '1';
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ahbo.hirq <= (others => '0');
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ahbo.hirq <= (others => '0');
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ahbo.hconfig <= hconfig;
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ahbo.hconfig <= hconfig;
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ahbo.hindex <= hindex;
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ahbo.hindex <= hindex;
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s_wdata <= ahbreadword(ahbi.hwdata, s_waddr(4 downto 2));
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process (clk) is
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process (clk) is
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procedure loadfile is
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procedure loadfile is
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file fd: text open read_mode is fname;
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file fd: text open read_mode is fname;
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variable lin: line;
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variable lin: line;
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variable c0, c1, c2, c3, c4, c5, c6, c7: character;
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variable c0, c1, c2, c3, c4, c5, c6, c7: character;
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variable n, t: integer;
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variable n, t: integer;
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variable adr: unsigned(31 downto 0);
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variable adr: unsigned(31 downto 0);
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variable dat: unsigned(31 downto 0);
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variable dat: unsigned(31 downto 0);
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begin
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begin
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for i in mem'range loop
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for i in mem'range loop
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mem(i) <= zero32;
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mem(i) <= zero32;
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end loop;
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end loop;
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while not endfile(fd) loop
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while not endfile(fd) loop
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readline(fd, lin);
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readline(fd, lin);
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read(lin, c0);
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read(lin, c0);
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if c0 = 'S' then
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if c0 = 'S' then
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read(lin, c0);
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read(lin, c0);
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if c0 = '1' or c0 = '2' or c0 = '3' then
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if c0 = '1' or c0 = '2' or c0 = '3' then
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t := to_integer(fromhex(c0 & ""));
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t := to_integer(fromhex(c0 & ""));
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read(lin, c0);
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read(lin, c0);
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read(lin, c1);
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read(lin, c1);
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n := to_integer(fromhex((c0, c1))) - t - 2;
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n := to_integer(fromhex((c0, c1))) - t - 2;
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assert n >= 0 and (n rem 4) = 0 report "invalid record length in SREC file";
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assert n >= 0 and (n rem 4) = 0 report "invalid record length in SREC file";
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read(lin, c0);
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read(lin, c0);
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read(lin, c1);
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read(lin, c1);
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read(lin, c2);
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read(lin, c2);
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read(lin, c3);
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read(lin, c3);
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if t = 2 then
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if t = 2 then
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read(lin, c4);
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read(lin, c4);
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read(lin, c5);
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read(lin, c5);
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adr := fromhex((c0, c1, c2, c3, c4, c5));
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adr := fromhex((c0, c1, c2, c3, c4, c5));
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elsif t = 3 then
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elsif t = 3 then
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read(lin, c4);
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read(lin, c4);
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read(lin, c5);
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read(lin, c5);
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read(lin, c6);
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read(lin, c6);
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read(lin, c7);
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read(lin, c7);
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adr := fromhex((c0, c1, c2, c3, c4, c5, c6, c7));
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adr := fromhex((c0, c1, c2, c3, c4, c5, c6, c7));
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else
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else
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adr := fromhex((c0, c1, c2, c3));
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adr := fromhex((c0, c1, c2, c3));
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end if;
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end if;
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assert adr(1 downto 0) = "00" report "invalid address in SREC file";
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assert adr(1 downto 0) = "00" report "invalid address in SREC file";
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for i in 0 to (n-4) / 4 loop
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for i in 0 to (n-4) / 4 loop
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read(lin, c0);
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read(lin, c0);
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read(lin, c1);
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read(lin, c1);
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read(lin, c2);
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read(lin, c2);
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read(lin, c3);
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read(lin, c3);
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read(lin, c4);
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read(lin, c4);
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read(lin, c5);
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read(lin, c5);
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read(lin, c6);
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read(lin, c6);
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read(lin, c7);
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read(lin, c7);
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dat := fromhex((c0, c1, c2, c3, c4, c5, c6, c7));
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dat := fromhex((c0, c1, c2, c3, c4, c5, c6, c7));
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mem(to_integer(adr(abits-1 downto 2)) + i) <= std_logic_vector(dat);
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mem(to_integer(adr(abits-1 downto 2)) + i) <= std_logic_vector(dat);
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end loop;
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end loop;
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end if;
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end if;
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end if;
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end if;
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end loop;
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end loop;
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report "Loaded AHBRAM contents";
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report "Loaded AHBRAM contents";
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end procedure;
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end procedure;
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variable wa: integer;
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variable wa: integer;
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begin
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begin
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if s_load = '1' then
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if s_load = '1' then
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-- Load RAM contents at start of simulation.
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-- Load RAM contents at start of simulation.
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s_load <= '0';
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s_load <= '0';
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loadfile;
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loadfile;
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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-- Clock tick.
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-- Clock tick.
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s_ready <= '1';
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s_ready <= '1';
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s_rdata <= mem(to_integer(unsigned(ahbi.haddr(abits-1 downto 2))));
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s_rdata <= mem(to_integer(unsigned(ahbi.haddr(abits-1 downto 2))));
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if ahbi.hready = '1' then
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if ahbi.hready = '1' then
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s_write <= ahbi.hsel(hindex) and ahbi.htrans(1) and ahbi.hwrite;
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s_write <= ahbi.hsel(hindex) and ahbi.htrans(1) and ahbi.hwrite;
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s_waddr <= ahbi.haddr;
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s_waddr <= ahbi.haddr;
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s_wsize <= ahbi.hsize;
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s_wsize <= ahbi.hsize;
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s_ready <= not (s_ready and ahbi.hsel(hindex) and ahbi.htrans(1) and ahbi.hwrite);
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s_ready <= not (s_ready and ahbi.hsel(hindex) and ahbi.htrans(1) and ahbi.hwrite);
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end if;
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end if;
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wa := to_integer(unsigned(s_waddr(abits-1 downto 2)));
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wa := to_integer(unsigned(s_waddr(abits-1 downto 2)));
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if s_write = '1' and s_ready = '1' then
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if s_write = '1' and s_ready = '1' then
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case s_wsize is
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case s_wsize is
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when HSIZE_BYTE =>
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when HSIZE_BYTE =>
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case s_waddr(1 downto 0) is
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case s_waddr(1 downto 0) is
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when "00" =>
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when "00" =>
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mem(wa)(31 downto 24) <= ahbi.hwdata(31 downto 24);
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mem(wa)(31 downto 24) <= s_wdata(31 downto 24);
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when "01" =>
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when "01" =>
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mem(wa)(23 downto 16) <= ahbi.hwdata(23 downto 16);
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mem(wa)(23 downto 16) <= s_wdata(23 downto 16);
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when "10" =>
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when "10" =>
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mem(wa)(15 downto 8) <= ahbi.hwdata(15 downto 8);
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mem(wa)(15 downto 8) <= s_wdata(15 downto 8);
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when others =>
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when others =>
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mem(wa)(7 downto 0) <= ahbi.hwdata(7 downto 0);
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mem(wa)(7 downto 0) <= s_wdata(7 downto 0);
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end case;
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end case;
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when HSIZE_HWORD =>
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when HSIZE_HWORD =>
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if s_waddr(1) = '1' then
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if s_waddr(1) = '1' then
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mem(wa)(15 downto 0) <= ahbi.hwdata(15 downto 0);
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mem(wa)(15 downto 0) <= s_wdata(15 downto 0);
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else
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else
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mem(wa)(31 downto 16) <= ahbi.hwdata(31 downto 16);
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mem(wa)(31 downto 16) <= s_wdata(31 downto 16);
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end if;
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end if;
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when others =>
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when others =>
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mem(wa) <= ahbi.hwdata;
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mem(wa) <= s_wdata;
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end case;
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end case;
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end if;
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end if;
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if rstn = '0' then
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if rstn = '0' then
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s_ready <= '0';
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s_ready <= '0';
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s_rdata <= (others => '0');
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s_rdata <= (others => '0');
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s_write <= '0';
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s_write <= '0';
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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-- pragma translate_off
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-- pragma translate_off
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bootmsg : report_version
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bootmsg : report_version
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generic map ( "ahbram_loadfile: 32-bit AHB RAM module, hindex=" & tost(hindex) & ", abits=" & tost(abits) & ", fname=" & fname);
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generic map ( "ahbram_loadfile: 32-bit AHB RAM module, hindex=" & tost(hindex) & ", abits=" & tost(abits) & ", fname=" & fname);
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-- pragma translate_on
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-- pragma translate_on
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end architecture ahbram_arch;
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end architecture ahbram_arch;
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