| Line 74... |
Line 74... |
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-- input generation
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-- input generation
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signal input_par: std_logic;
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signal input_par: std_logic;
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signal input_idle: std_logic;
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signal input_idle: std_logic;
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signal input_pattern: integer := 0;
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signal input_pattern: integer := 0;
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signal input_strobeflip: std_logic := '0';
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-- interconnect signals
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-- interconnect signals
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signal s_linki: spw_link_in_type;
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signal s_linki: spw_link_in_type;
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signal s_linko: spw_link_out_type;
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signal s_linko: spw_link_out_type;
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signal s_rxen: std_logic;
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signal s_rxen: std_logic;
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| Line 356... |
Line 357... |
-- Generate input data.
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-- Generate input data.
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process is
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process is
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procedure input_reset is
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procedure input_reset is
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begin
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begin
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spw_di <= '0';
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spw_di <= '0';
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spw_si <= '0';
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spw_si <= input_strobeflip;
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input_par <= '0';
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input_par <= '0';
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end procedure;
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end procedure;
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procedure genbit(b: std_logic) is
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procedure genbit(b: std_logic) is
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begin
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begin
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spw_si <= not (spw_si xor spw_di xor b);
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spw_si <= not (spw_si xor spw_di xor b);
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| Line 471... |
Line 472... |
genfct;
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genfct;
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genfct;
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genfct;
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while input_pattern = 9 loop
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while input_pattern = 9 loop
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genesc; genfct;
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genesc; genfct;
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end loop;
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end loop;
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elsif input_pattern = 10 then
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-- data and strobe both high
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spw_di <= '1';
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spw_si <= not input_strobeflip;
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wait until input_pattern /= 10;
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else
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else
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assert false;
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assert false;
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end if;
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end if;
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end loop;
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end loop;
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end process;
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end process;
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| Line 526... |
Line 532... |
wait for startwait;
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wait for startwait;
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-- Initialize.
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-- Initialize.
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rst <= '1';
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rst <= '1';
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input_pattern <= 0;
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input_pattern <= 0;
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input_strobeflip <= '0';
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sys_clock_enable <= '1';
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sys_clock_enable <= '1';
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output_collect <= '0';
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output_collect <= '0';
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-- Say hello
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-- Say hello
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report "Starting spwlink test bench";
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report "Starting spwlink test bench";
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| Line 971... |
Line 978... |
output_collect <= '0';
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output_collect <= '0';
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input_pattern <= 0;
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input_pattern <= 0;
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linkstart <= '0';
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linkstart <= '0';
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wait until rising_edge(sysclk);
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wait until rising_edge(sysclk);
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-- Test 15: start with wrong strobe polarity.
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input_strobeflip <= '1';
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linkstart <= '1';
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rxroom <= "001000";
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input_pattern <= 1;
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wait on started, connecting, running for 20 us;
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assert (started = '1') and (connecting = '0') and (running = '0')
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report " 15. weird_strobe (Started)";
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linkstart <= '0';
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wait until rising_edge(sysclk);
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input_pattern <= 9;
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wait on started, connecting, running, errany for 20 * inbit_period;
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assert (started = '0') and (connecting = '1') and (running = '0') and (errany = '0')
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report " 15. weird_strobe (Connecting)";
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wait on started, connecting, running, errany for 200 ns + 24 * inbit_period;
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assert (started = '0') and (connecting = '0') and (running = '1') and (errany = '0')
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report " 15. weird_strobe (Run)";
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linkdis <= '1';
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wait until rising_edge(sysclk);
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input_pattern <= 0;
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input_strobeflip <= '0';
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wait until input_idle = '1';
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linkdis <= '0';
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wait until rising_edge(sysclk);
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-- Test 16: start with wrong data polarity.
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input_pattern <= 10;
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linkstart <= '1';
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rxroom <= "001111";
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wait on started, connecting, running for 25 us;
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assert (started = '1') and (running = '0')
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report " 16. weird_data (started)";
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if spw_so = '0' then
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wait on started, connecting, running, spw_do, spw_so for 1.2 us;
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end if;
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assert (started = '1') and (connecting = '0') and (running = '0') and
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(spw_do = '0') and (spw_so = '1')
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report " 16. weird_data (SPW strobe)";
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output_collect <= '1';
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wait on started, connecting, running for (7.1 * outbit_period);
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assert (started = '1') and (running = '0')
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report " 16. weird_data (state 2)";
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assert (output_ptr = 8) and (output_bits(0 to 7) = "01110100")
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report " 16. weird_data (NULL 1)";
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-- got the first NULL, wait for the second one ...
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wait on started, connecting, running for (8.0 * outbit_period);
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assert (started = '1') and (running = '0')
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report " 16. weird_data (state 3)";
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assert (output_ptr = 16) and (output_bits(8 to 15) = "01110100")
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report " 16. weird_data (NULL 2)";
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output_collect <= '0';
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linkstart <= '0';
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linkdis <= '1';
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input_pattern <= 0;
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wait until rising_edge(sysclk);
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linkdis <= '0';
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wait until rising_edge(sysclk);
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-- Stop simulation
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-- Stop simulation
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input_pattern <= 0;
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input_pattern <= 0;
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wait for 100 us;
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wait for 100 us;
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sys_clock_enable <= '0';
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sys_clock_enable <= '0';
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report "Done.";
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report "Done.";
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