| Line 162... |
Line 162... |
--
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--
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-- Combinatorial process
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-- Combinatorial process
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--
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--
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process (r, rstn, msti, ahbi) is
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process (r, rstn, msti, ahbi) is
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variable v: regs_type;
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variable v: regs_type;
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variable v_hrdata: std_logic_vector(31 downto 0);
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variable v_burstreq: std_logic;
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variable v_burstreq: std_logic;
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variable v_burstack: std_logic;
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variable v_burstack: std_logic;
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variable v_rxfifo_read: std_logic;
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variable v_rxfifo_read: std_logic;
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variable v_txfifo_write: std_logic;
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variable v_txfifo_write: std_logic;
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variable v_txfifo_wdata: std_logic_vector(35 downto 0);
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variable v_txfifo_wdata: std_logic_vector(35 downto 0);
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begin
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begin
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v := r;
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v := r;
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-- Decode AHB data bus (64-bit AHB compatibility).
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v_hrdata := ahbreadword(ahbi.hrdata);
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-- Assume no burst request.
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-- Assume no burst request.
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v_burstreq := '0';
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v_burstreq := '0';
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-- Detect request from burst state machine for next data word.
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-- Detect request from burst state machine for next data word.
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v_burstack := ahbi.hready and
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v_burstack := ahbi.hready and
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| Line 181... |
Line 185... |
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-- Assume no fifo activity; take data for TX fifo from AHB bus.
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-- Assume no fifo activity; take data for TX fifo from AHB bus.
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v_rxfifo_read := '0';
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v_rxfifo_read := '0';
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v_txfifo_write := '0';
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v_txfifo_write := '0';
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v_txfifo_wdata(35 downto 32) := (others => '0');
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v_txfifo_wdata(35 downto 32) := (others => '0');
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v_txfifo_wdata(31 downto 0) := ahbi.hrdata;
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v_txfifo_wdata(31 downto 0) := v_hrdata;
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-- Reset registers for interrupts and descriptor updates.
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-- Reset registers for interrupts and descriptor updates.
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v.int_rxdesc := '0';
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v.int_rxdesc := '0';
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v.int_txdesc := '0';
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v.int_txdesc := '0';
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v.int_rxpacket := '0';
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v.int_rxpacket := '0';
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| Line 259... |
Line 263... |
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when st_rxgetdesc =>
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when st_rxgetdesc =>
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-- Read RX descriptor flags from memory.
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-- Read RX descriptor flags from memory.
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v_burstreq := '1';
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v_burstreq := '1';
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v.hwrite := '0';
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v.hwrite := '0';
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v.rxdes_len := ahbi.hrdata(15 downto 2);
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v.rxdes_len := v_hrdata(15 downto 2);
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v.rxdes_en := ahbi.hrdata(16);
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v.rxdes_en := v_hrdata(16);
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v.rxdes_wr := ahbi.hrdata(17);
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v.rxdes_wr := v_hrdata(17);
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v.rxdes_ie := ahbi.hrdata(18);
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v.rxdes_ie := v_hrdata(18);
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v.rxdes_eop := '0';
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v.rxdes_eop := '0';
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v.rxdes_eep := '0';
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v.rxdes_eep := '0';
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v.rxdes_pos := (others => '0');
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v.rxdes_pos := (others => '0');
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if v_burstack = '1' then
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if v_burstack = '1' then
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-- Got descriptor flags.
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-- Got descriptor flags.
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| Line 274... |
Line 278... |
v.mstate := st_rxgetptr;
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v.mstate := st_rxgetptr;
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end if;
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end if;
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when st_rxgetptr =>
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when st_rxgetptr =>
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-- Read RX data pointer from memory.
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-- Read RX data pointer from memory.
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v.rxaddr := ahbi.hrdata(31 downto 2);
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v.rxaddr := v_hrdata(31 downto 2);
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v.haddr := ahbi.hrdata(31 downto 2);
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v.haddr := v_hrdata(31 downto 2);
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v.firstword := '1';
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v.firstword := '1';
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if v_burstack = '1' then
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if v_burstack = '1' then
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-- Got data pointer.
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-- Got data pointer.
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if r.rxdes_en = '1' then
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if r.rxdes_en = '1' then
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-- Start transfer.
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-- Start transfer.
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| Line 381... |
Line 385... |
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when st_txgetdesc =>
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when st_txgetdesc =>
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-- Read TX descriptor flags from memory.
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-- Read TX descriptor flags from memory.
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v_burstreq := '1';
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v_burstreq := '1';
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v.hwrite := '0';
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v.hwrite := '0';
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v.txdes_len := ahbi.hrdata(15 downto 0);
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v.txdes_len := v_hrdata(15 downto 0);
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v.txdes_en := ahbi.hrdata(16);
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v.txdes_en := v_hrdata(16);
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v.txdes_wr := ahbi.hrdata(17);
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v.txdes_wr := v_hrdata(17);
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v.txdes_ie := ahbi.hrdata(18);
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v.txdes_ie := v_hrdata(18);
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v.txdes_eop := ahbi.hrdata(20);
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v.txdes_eop := v_hrdata(20);
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v.txdes_eep := ahbi.hrdata(21);
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v.txdes_eep := v_hrdata(21);
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if v_burstack = '1' then
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if v_burstack = '1' then
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-- Got descriptor flags.
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-- Got descriptor flags.
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v_burstreq := '0';
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v_burstreq := '0';
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v.mstate := st_txgetptr;
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v.mstate := st_txgetptr;
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end if;
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end if;
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when st_txgetptr =>
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when st_txgetptr =>
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-- Read TX data pointer from memory.
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-- Read TX data pointer from memory.
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v.txaddr := ahbi.hrdata(31 downto 2);
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v.txaddr := v_hrdata(31 downto 2);
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if v_burstack = '1' then
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if v_burstack = '1' then
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-- Got data pointer.
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-- Got data pointer.
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if r.txdes_en = '1' then
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if r.txdes_en = '1' then
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-- Start transfer.
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-- Start transfer.
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if unsigned(r.txdes_len) = 0 then
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if unsigned(r.txdes_len) = 0 then
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| Line 410... |
Line 414... |
v.txdesc_next := '1';
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v.txdesc_next := '1';
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v.mstate := st_txputdesc;
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v.mstate := st_txputdesc;
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else
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else
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v_burstreq := '1';
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v_burstreq := '1';
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v.hwrite := '0';
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v.hwrite := '0';
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v.haddr := ahbi.hrdata(31 downto 2);
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v.haddr := v_hrdata(31 downto 2);
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if unsigned(r.txdes_len) <= 4 then
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if unsigned(r.txdes_len) <= 4 then
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-- Transfer only one word.
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-- Transfer only one word.
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v.mstate := st_txfinal;
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v.mstate := st_txfinal;
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else
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else
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v.mstate := st_txtransfer;
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v.mstate := st_txtransfer;
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| Line 681... |
Line 685... |
else
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else
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ahbo.htrans <= HTRANS_IDLE;
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ahbo.htrans <= HTRANS_IDLE;
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end if;
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end if;
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ahbo.haddr <= r.haddr & "00";
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ahbo.haddr <= r.haddr & "00";
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ahbo.hwrite <= r.hwrite;
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ahbo.hwrite <= r.hwrite;
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ahbo.hwdata <= r.hwdata;
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ahbo.hwdata <= ahbdrivedata(r.hwdata);
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ahbo.hlock <= '0'; -- never lock the bus
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ahbo.hlock <= '0'; -- never lock the bus
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ahbo.hsize <= HSIZE_WORD; -- always 32-bit words
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ahbo.hsize <= HSIZE_WORD; -- always 32-bit words
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ahbo.hburst <= HBURST_INCR; -- undetermined incremental burst
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ahbo.hburst <= HBURST_INCR; -- undetermined incremental burst
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ahbo.hprot <= "0011"; -- not cacheable, privileged, data
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ahbo.hprot <= "0011"; -- not cacheable, privileged, data
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ahbo.hirq <= (others => '0'); -- no interrupts via AHB bus
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ahbo.hirq <= (others => '0'); -- no interrupts via AHB bus
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