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[/] [spacewire_light/] [trunk/] [rtl/] [vhdl/] [spwahbmst.vhd] - Diff between revs 5 and 6

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Rev 5 Rev 6
Line 333... Line 333...
                       unsigned(r.rxdes_len) = 1 then
                       unsigned(r.rxdes_len) = 1 then
                        v_burstreq  := '0';
                        v_burstreq  := '0';
                        v.mstate    := st_rxfinal;
                        v.mstate    := st_rxfinal;
                    end if;
                    end if;
                    -- Stop at max burst length boundary.
                    -- Stop at max burst length boundary.
                    if (andv(r.rxaddr(maxburst+2 downto 2)) = '1') then
                    if (andv(r.rxaddr(maxburst+1 downto 2)) = '1') then
                        v_burstreq  := '0';
                        v_burstreq  := '0';
                        v.mstate    := st_rxfinal;
                        v.mstate    := st_rxfinal;
                    end if;
                    end if;
                end if;
                end if;
 
 
Line 436... Line 436...
                    v_txfifo_write  := '1';
                    v_txfifo_write  := '1';
                    -- Update pointers.
                    -- Update pointers.
                    v.txdes_len := std_logic_vector(unsigned(r.txdes_len) - 4);
                    v.txdes_len := std_logic_vector(unsigned(r.txdes_len) - 4);
                    v.txaddr    := std_logic_vector(unsigned(r.txaddr) + 1);
                    v.txaddr    := std_logic_vector(unsigned(r.txaddr) + 1);
                    -- Handle end of burst/transfer.
                    -- Handle end of burst/transfer.
                    if andv(r.txaddr(maxburst+2 downto 2)) = '1' then
                    if andv(r.txaddr(maxburst+1 downto 2)) = '1' then
                        -- This was the last data cycle before the max burst boundary.
                        -- This was the last data cycle before the max burst boundary.
                        -- Go through st_idle to pick up more work.
                        -- Go through st_idle to pick up more work.
                        v_burstreq  := '0';
                        v_burstreq  := '0';
                        v.mstate    := st_idle;
                        v.mstate    := st_idle;
                    elsif msti.txfifo_nxfull = '1' then
                    elsif msti.txfifo_nxfull = '1' then
Line 449... Line 449...
                        v.mstate    := st_txskip;
                        v.mstate    := st_txskip;
                    elsif unsigned(r.txdes_len) <= 8 then
                    elsif unsigned(r.txdes_len) <= 8 then
                        -- Stop at end of requested length (one more data cycle).
                        -- Stop at end of requested length (one more data cycle).
                        v_burstreq  := '0';
                        v_burstreq  := '0';
                        v.mstate    := st_txfinal;
                        v.mstate    := st_txfinal;
                    elsif andv(r.txaddr(maxburst+2 downto 3)) = '1' then
                    elsif andv(r.txaddr(maxburst+1 downto 3)) = '1' then
                        -- Stop at max burst length boundary (one more data cycle).
                        -- Stop at max burst length boundary (one more data cycle).
                        v_burstreq  := '0';
                        v_burstreq  := '0';
                    end if;
                    end if;
                else
                else
                    if andv(r.txaddr(maxburst+2 downto 2)) = '1' then
                    if andv(r.txaddr(maxburst+1 downto 2)) = '1' then
                        -- Stop at max burst length boundary (just one more data cycle).
                        -- Stop at max burst length boundary (just one more data cycle).
                        v_burstreq  := '0';
                        v_burstreq  := '0';
                    end if;
                    end if;
                end if;
                end if;
 
 
Line 595... Line 595...
                -- First address cycle.
                -- First address cycle.
                -- (htrans = HTRANS_NONSEQ)
                -- (htrans = HTRANS_NONSEQ)
                v.hbusreq   := '1';
                v.hbusreq   := '1';
                if ahbi.hready = '1' then
                if ahbi.hready = '1' then
                    -- Increment address and continue burst in bs_active.
                    -- Increment address and continue burst in bs_active.
                    v.haddr     := std_logic_vector(unsigned(r.haddr) + 1);
                    v.haddr(maxburst+1 downto 2) := std_logic_vector(unsigned(r.haddr(maxburst+1 downto 2)) + 1);
                    v.burststat := bs_active;
                    v.burststat := bs_active;
                    -- Stop burst when application ends the transfer.
                    -- Stop burst when application ends the transfer.
                    v.hbusreq   := v_burstreq;
                    v.hbusreq   := v_burstreq;
                    if v_burstreq = '0' then
                    if v_burstreq = '0' then
                        v.burststat := bs_end;
                        v.burststat := bs_end;
Line 614... Line 614...
                -- Continue burst.
                -- Continue burst.
                -- (htrans = HTRANS_SEQ)
                -- (htrans = HTRANS_SEQ)
                v.hbusreq   := '1';
                v.hbusreq   := '1';
                if ahbi.hresp /= HRESP_OKAY then
                if ahbi.hresp /= HRESP_OKAY then
                    -- Error response from slave.
                    -- Error response from slave.
                    v.haddr     := std_logic_vector(unsigned(r.haddr) - 1);
                    v.haddr(maxburst+1 downto 2) := std_logic_vector(unsigned(r.haddr(maxburst+1 downto 2)) - 1);
                    if ahbi.hresp = HRESP_ERROR then
                    if ahbi.hresp = HRESP_ERROR then
                        -- Permanent error.
                        -- Permanent error.
                        v.ahberror  := '1';
                        v.ahberror  := '1';
                        v.hbusreq   := '0';
                        v.hbusreq   := '0';
                    else
                    else
Line 626... Line 626...
                        v.hbusreq   := '1';
                        v.hbusreq   := '1';
                    end if;
                    end if;
                    v.burststat := bs_idle;
                    v.burststat := bs_idle;
                elsif ahbi.hready = '1' then
                elsif ahbi.hready = '1' then
                    -- Increment address.
                    -- Increment address.
                    v.haddr     := std_logic_vector(unsigned(r.haddr) + 1);
                    v.haddr(maxburst+1 downto 2) := std_logic_vector(unsigned(r.haddr(maxburst+1 downto 2)) + 1);
                    -- Stop burst when application ends the transfer.
                    -- Stop burst when application ends the transfer.
                    v.hbusreq   := v_burstreq;
                    v.hbusreq   := v_burstreq;
                    if v_burstreq = '0' then
                    if v_burstreq = '0' then
                        v.burststat := bs_end;
                        v.burststat := bs_end;
                    end if;
                    end if;
Line 644... Line 644...
                -- Last data cycle of burst.
                -- Last data cycle of burst.
                -- (htrans = HTRANS_IDLE)
                -- (htrans = HTRANS_IDLE)
                v.hbusreq   := r.hbusreq or v_burstreq;
                v.hbusreq   := r.hbusreq or v_burstreq;
                if ahbi.hresp /= HRESP_OKAY then
                if ahbi.hresp /= HRESP_OKAY then
                    -- Error response from slave.
                    -- Error response from slave.
                    v.haddr     := std_logic_vector(unsigned(r.haddr) - 1);
                    v.haddr(maxburst+1 downto 2) := std_logic_vector(unsigned(r.haddr(maxburst+1 downto 2)) - 1);
                    if ahbi.hresp = HRESP_ERROR then
                    if ahbi.hresp = HRESP_ERROR then
                        -- Permanent error.
                        -- Permanent error.
                        v.ahberror  := '1';
                        v.ahberror  := '1';
                        v.hbusreq   := '0';
                        v.hbusreq   := '0';
                    else
                    else

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