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[/] [spacewire_light/] [trunk/] [rtl/] [vhdl/] [spwamba.vhd] - Diff between revs 5 and 6

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Rev 5 Rev 6
Line 308... Line 308...
    signal recv_rxen:       std_logic;
    signal recv_rxen:       std_logic;
    signal recvo:           spw_recv_out_type;
    signal recvo:           spw_recv_out_type;
    signal recv_inact:      std_logic;
    signal recv_inact:      std_logic;
    signal recv_inbvalid:   std_logic;
    signal recv_inbvalid:   std_logic;
    signal recv_inbits:     std_logic_vector(rxchunk-1 downto 0);
    signal recv_inbits:     std_logic_vector(rxchunk-1 downto 0);
 
    signal xmit_rst:        std_logic;
    signal xmiti:           spw_xmit_in_type;
    signal xmiti:           spw_xmit_in_type;
    signal xmito:           spw_xmit_out_type;
    signal xmito:           spw_xmit_out_type;
    signal xmit_divcnt:     std_logic_vector(7 downto 0);
    signal xmit_divcnt:     std_logic_vector(7 downto 0);
 
    signal link_rst:        std_logic;
    signal linki:           spw_link_in_type;
    signal linki:           spw_link_in_type;
    signal linko:           spw_link_out_type;
    signal linko:           spw_link_out_type;
    signal msti:            spw_ahbmst_in_type;
    signal msti:            spw_ahbmst_in_type;
    signal msto:            spw_ahbmst_out_type;
    signal msto:            spw_ahbmst_out_type;
    signal ahbmst_rstn:     std_logic;
    signal ahbmst_rstn:     std_logic;
    signal s_rst:           std_logic;
 
 
 
    -- Memory interface signals.
    -- Memory interface signals.
    signal s_rxfifo_raddr:  std_logic_vector(rxfifosize-1 downto 0);
    signal s_rxfifo_raddr:  std_logic_vector(rxfifosize-1 downto 0);
    signal s_rxfifo_rdata:  std_logic_vector(35 downto 0);
    signal s_rxfifo_rdata:  std_logic_vector(35 downto 0);
    signal s_rxfifo_wen:    std_logic;
    signal s_rxfifo_wen:    std_logic;
Line 350... Line 351...
    link_inst: spwlink
    link_inst: spwlink
        generic map (
        generic map (
            reset_time  => reset_time )
            reset_time  => reset_time )
        port map (
        port map (
            clk         => clk,
            clk         => clk,
            rst         => s_rst,
            rst         => link_rst,
            linki       => linki,
            linki       => linki,
            linko       => linko,
            linko       => linko,
            rxen        => recv_rxen,
            rxen        => recv_rxen,
            recvo       => recvo,
            recvo       => recvo,
            xmiti       => xmiti,
            xmiti       => xmiti,
Line 403... Line 404...
    -- Instantiate transmitter.
    -- Instantiate transmitter.
    xmit_sel0: if tximpl = impl_generic generate
    xmit_sel0: if tximpl = impl_generic generate
        xmit_inst: spwxmit
        xmit_inst: spwxmit
            port map (
            port map (
                clk     => clk,
                clk     => clk,
                rst     => s_rst,
                rst     => xmit_rst,
                divcnt  => xmit_divcnt,
                divcnt  => xmit_divcnt,
                xmiti   => xmiti,
                xmiti   => xmiti,
                xmito   => xmito,
                xmito   => xmito,
                spw_do  => spw_do,
                spw_do  => spw_do,
                spw_so  => spw_so );
                spw_so  => spw_so );
Line 415... Line 416...
    xmit_sel1: if tximpl = impl_fast generate
    xmit_sel1: if tximpl = impl_fast generate
        xmit_fast_inst: spwxmit_fast
        xmit_fast_inst: spwxmit_fast
            port map (
            port map (
                clk     => clk,
                clk     => clk,
                txclk   => txclk,
                txclk   => txclk,
                rst     => s_rst,
                rst     => xmit_rst,
                divcnt  => xmit_divcnt,
                divcnt  => xmit_divcnt,
                xmiti   => xmiti,
                xmiti   => xmiti,
                xmito   => xmito,
                xmito   => xmito,
                spw_do  => spw_do,
                spw_do  => spw_do,
                spw_so  => spw_so );
                spw_so  => spw_so );
Line 594... Line 595...
        if v_tmprxroom > 63 then
        if v_tmprxroom > 63 then
            -- at least 64 bytes room.
            -- at least 64 bytes room.
            v.rxroom    := "111111";
            v.rxroom    := "111111";
        else
        else
            -- less than 64 bytes room.
            -- less than 64 bytes room.
            v.rxroom    := std_logic_vector(v_tmprxroom(5 downto 0));
            -- If linko.rxchar = '1', decrease rxroom by one to account for
 
            -- the pipeline delay through r.rxfifo_write.
 
            v.rxroom    := std_logic_vector(v_tmprxroom(5 downto 0) -
 
                             to_unsigned(conv_integer(linko.rxchar), 6));
        end if;
        end if;
 
 
        -- Update TX fifo write pointer.
        -- Update TX fifo write pointer.
        if msto.txfifo_write = '1' then
        if msto.txfifo_write = '1' then
            -- write one word.
            -- write one word.
Line 614... Line 618...
        if unsigned(r.txfifo_raddr) - unsigned(r.txfifo_waddr) = to_unsigned(2, txfifosize) then
        if unsigned(r.txfifo_raddr) - unsigned(r.txfifo_waddr) = to_unsigned(2, txfifosize) then
            -- currently exactly 2 words left.
            -- currently exactly 2 words left.
            v.txfifo_nxfull := msto.txfifo_write;
            v.txfifo_nxfull := msto.txfifo_write;
        end if;
        end if;
 
 
        -- Detect TX fifo more than 3/4 full.
        -- Detect TX fifo high water mark.
        if unsigned(r.txfifo_raddr) - unsigned(r.txfifo_waddr) = to_unsigned(2**(txfifosize-2), txfifosize) then
        if txfifosize > maxburst then
            -- currently exactly 3/4 full.
            -- Indicate high water when there is no room for a maximum burst.
 
            if unsigned(r.txfifo_raddr) - unsigned(r.txfifo_waddr) = to_unsigned(2**maxburst + 1, txfifosize) then
 
                -- currently room for exactly one maximum burst.
            v.txfifo_highw  := msto.txfifo_write;
            v.txfifo_highw  := msto.txfifo_write;
        end if;
        end if;
 
        else
 
            -- Indicate high water when more than half full.
 
            if unsigned(r.txfifo_raddr) - unsigned(r.txfifo_waddr) = to_unsigned(2**(txfifosize-1), txfifosize) then
 
                -- currently exactly half full.
 
                v.txfifo_highw  := msto.txfifo_write;
 
            end if;
 
        end if;
 
 
        -- Update descriptor pointers.
        -- Update descriptor pointers.
        if msto.rxdesc_next = '1' then
        if msto.rxdesc_next = '1' then
            if msto.rxdesc_wrap = '1' then
            if msto.rxdesc_wrap = '1' then
                v.rxdesc_ptr(desctablesize+2 downto 3) := (others => '0');
                v.rxdesc_ptr(desctablesize+2 downto 3) := (others => '0');
Line 825... Line 838...
        apbo.pconfig    <= pconfig;
        apbo.pconfig    <= pconfig;
        apbo.pindex     <= pindex;
        apbo.pindex     <= pindex;
 
 
        -- Reset components.
        -- Reset components.
        ahbmst_rstn     <= rstn and (not r.ctl_reset) and (not r.ctl_resetdma);
        ahbmst_rstn     <= rstn and (not r.ctl_reset) and (not r.ctl_resetdma);
        s_rst           <= (not rstn) or r.ctl_reset;
        link_rst        <= (not rstn) or r.ctl_reset;
 
        xmit_rst        <= not rstn;
 
 
        -- Clear TX fifo on cancel request.
        -- Clear TX fifo on cancel request.
        if r.ctl_txcancel = '1' then
        if r.ctl_txcancel = '1' then
            v.txfifo_raddr  := (others => '0');
            v.txfifo_raddr  := (others => '0');
            v.txfifo_waddr  := (others => '0');
            v.txfifo_waddr  := (others => '0');

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