| Line 308... |
Line 308... |
signal recv_rxen: std_logic;
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signal recv_rxen: std_logic;
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signal recvo: spw_recv_out_type;
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signal recvo: spw_recv_out_type;
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signal recv_inact: std_logic;
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signal recv_inact: std_logic;
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signal recv_inbvalid: std_logic;
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signal recv_inbvalid: std_logic;
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signal recv_inbits: std_logic_vector(rxchunk-1 downto 0);
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signal recv_inbits: std_logic_vector(rxchunk-1 downto 0);
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signal xmit_rst: std_logic;
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signal xmiti: spw_xmit_in_type;
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signal xmiti: spw_xmit_in_type;
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signal xmito: spw_xmit_out_type;
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signal xmito: spw_xmit_out_type;
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signal xmit_divcnt: std_logic_vector(7 downto 0);
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signal xmit_divcnt: std_logic_vector(7 downto 0);
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signal link_rst: std_logic;
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signal linki: spw_link_in_type;
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signal linki: spw_link_in_type;
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signal linko: spw_link_out_type;
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signal linko: spw_link_out_type;
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signal msti: spw_ahbmst_in_type;
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signal msti: spw_ahbmst_in_type;
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signal msto: spw_ahbmst_out_type;
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signal msto: spw_ahbmst_out_type;
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signal ahbmst_rstn: std_logic;
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signal ahbmst_rstn: std_logic;
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signal s_rst: std_logic;
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-- Memory interface signals.
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-- Memory interface signals.
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signal s_rxfifo_raddr: std_logic_vector(rxfifosize-1 downto 0);
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signal s_rxfifo_raddr: std_logic_vector(rxfifosize-1 downto 0);
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signal s_rxfifo_rdata: std_logic_vector(35 downto 0);
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signal s_rxfifo_rdata: std_logic_vector(35 downto 0);
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signal s_rxfifo_wen: std_logic;
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signal s_rxfifo_wen: std_logic;
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| Line 350... |
Line 351... |
link_inst: spwlink
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link_inst: spwlink
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generic map (
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generic map (
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reset_time => reset_time )
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reset_time => reset_time )
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port map (
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port map (
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clk => clk,
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clk => clk,
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rst => s_rst,
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rst => link_rst,
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linki => linki,
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linki => linki,
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linko => linko,
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linko => linko,
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rxen => recv_rxen,
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rxen => recv_rxen,
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recvo => recvo,
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recvo => recvo,
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xmiti => xmiti,
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xmiti => xmiti,
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| Line 403... |
Line 404... |
-- Instantiate transmitter.
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-- Instantiate transmitter.
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xmit_sel0: if tximpl = impl_generic generate
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xmit_sel0: if tximpl = impl_generic generate
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xmit_inst: spwxmit
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xmit_inst: spwxmit
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port map (
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port map (
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clk => clk,
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clk => clk,
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rst => s_rst,
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rst => xmit_rst,
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divcnt => xmit_divcnt,
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divcnt => xmit_divcnt,
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xmiti => xmiti,
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xmiti => xmiti,
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xmito => xmito,
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xmito => xmito,
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spw_do => spw_do,
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spw_do => spw_do,
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spw_so => spw_so );
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spw_so => spw_so );
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| Line 415... |
Line 416... |
xmit_sel1: if tximpl = impl_fast generate
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xmit_sel1: if tximpl = impl_fast generate
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xmit_fast_inst: spwxmit_fast
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xmit_fast_inst: spwxmit_fast
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port map (
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port map (
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clk => clk,
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clk => clk,
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txclk => txclk,
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txclk => txclk,
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rst => s_rst,
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rst => xmit_rst,
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divcnt => xmit_divcnt,
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divcnt => xmit_divcnt,
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xmiti => xmiti,
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xmiti => xmiti,
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xmito => xmito,
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xmito => xmito,
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spw_do => spw_do,
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spw_do => spw_do,
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spw_so => spw_so );
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spw_so => spw_so );
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| Line 594... |
Line 595... |
if v_tmprxroom > 63 then
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if v_tmprxroom > 63 then
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-- at least 64 bytes room.
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-- at least 64 bytes room.
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v.rxroom := "111111";
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v.rxroom := "111111";
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else
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else
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-- less than 64 bytes room.
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-- less than 64 bytes room.
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v.rxroom := std_logic_vector(v_tmprxroom(5 downto 0));
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-- If linko.rxchar = '1', decrease rxroom by one to account for
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-- the pipeline delay through r.rxfifo_write.
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v.rxroom := std_logic_vector(v_tmprxroom(5 downto 0) -
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to_unsigned(conv_integer(linko.rxchar), 6));
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end if;
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end if;
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-- Update TX fifo write pointer.
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-- Update TX fifo write pointer.
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if msto.txfifo_write = '1' then
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if msto.txfifo_write = '1' then
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-- write one word.
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-- write one word.
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| Line 614... |
Line 618... |
if unsigned(r.txfifo_raddr) - unsigned(r.txfifo_waddr) = to_unsigned(2, txfifosize) then
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if unsigned(r.txfifo_raddr) - unsigned(r.txfifo_waddr) = to_unsigned(2, txfifosize) then
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-- currently exactly 2 words left.
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-- currently exactly 2 words left.
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v.txfifo_nxfull := msto.txfifo_write;
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v.txfifo_nxfull := msto.txfifo_write;
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end if;
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end if;
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-- Detect TX fifo more than 3/4 full.
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-- Detect TX fifo high water mark.
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if unsigned(r.txfifo_raddr) - unsigned(r.txfifo_waddr) = to_unsigned(2**(txfifosize-2), txfifosize) then
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if txfifosize > maxburst then
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-- currently exactly 3/4 full.
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-- Indicate high water when there is no room for a maximum burst.
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if unsigned(r.txfifo_raddr) - unsigned(r.txfifo_waddr) = to_unsigned(2**maxburst + 1, txfifosize) then
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-- currently room for exactly one maximum burst.
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v.txfifo_highw := msto.txfifo_write;
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v.txfifo_highw := msto.txfifo_write;
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end if;
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end if;
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else
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-- Indicate high water when more than half full.
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if unsigned(r.txfifo_raddr) - unsigned(r.txfifo_waddr) = to_unsigned(2**(txfifosize-1), txfifosize) then
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-- currently exactly half full.
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v.txfifo_highw := msto.txfifo_write;
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end if;
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end if;
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-- Update descriptor pointers.
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-- Update descriptor pointers.
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if msto.rxdesc_next = '1' then
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if msto.rxdesc_next = '1' then
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if msto.rxdesc_wrap = '1' then
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if msto.rxdesc_wrap = '1' then
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v.rxdesc_ptr(desctablesize+2 downto 3) := (others => '0');
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v.rxdesc_ptr(desctablesize+2 downto 3) := (others => '0');
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| Line 825... |
Line 838... |
apbo.pconfig <= pconfig;
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apbo.pconfig <= pconfig;
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apbo.pindex <= pindex;
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apbo.pindex <= pindex;
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-- Reset components.
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-- Reset components.
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ahbmst_rstn <= rstn and (not r.ctl_reset) and (not r.ctl_resetdma);
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ahbmst_rstn <= rstn and (not r.ctl_reset) and (not r.ctl_resetdma);
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s_rst <= (not rstn) or r.ctl_reset;
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link_rst <= (not rstn) or r.ctl_reset;
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xmit_rst <= not rstn;
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-- Clear TX fifo on cancel request.
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-- Clear TX fifo on cancel request.
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if r.ctl_txcancel = '1' then
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if r.ctl_txcancel = '1' then
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v.txfifo_raddr := (others => '0');
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v.txfifo_raddr := (others => '0');
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v.txfifo_waddr := (others => '0');
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v.txfifo_waddr := (others => '0');
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