Assembler report for spw_fifo_ulight
Mon Feb 5 00:57:44 2018
Quartus Prime Version 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition
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; Table of Contents ;
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1. Legal Notice
2. Assembler Summary
3. Assembler Settings
4. Assembler Generated Files
5. Assembler Device Options: spw_fifo_ulight.sof
6. Assembler Messages
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; Legal Notice ;
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Copyright (C) 2017 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Mon Feb 5 00:57:44 2018 ;
; Revision Name ; spw_fifo_ulight ;
; Top-level Entity Name ; SPW_ULIGHT_FIFO ;
; Family ; Cyclone V ;
; Device ; 5CSEMA4U23C6 ;
+-----------------------+---------------------------------------+
+----------------------------------+
; Assembler Settings ;
+--------+---------+---------------+
; Option ; Setting ; Default Value ;
+--------+---------+---------------+
+---------------------------------------------------------------------------------------------------------------------------------------+
; Assembler Generated Files ;
+---------------------------------------------------------------------------------------------------------------------------------------+
; File Name ;
+---------------------------------------------------------------------------------------------------------------------------------------+
; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/output_files/spw_fifo_ulight.sof ;
+---------------------------------------------------------------------------------------------------------------------------------------+
+-----------------------------------------------+
; Assembler Device Options: spw_fifo_ulight.sof ;
+----------------+------------------------------+
; Option ; Setting ;
+----------------+------------------------------+
; JTAG usercode ; 0x00C20F9D ;
; Checksum ; 0x00C20F9D ;
+----------------+------------------------------+
+--------------------+
; Assembler Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus Prime Assembler
Info: Version 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition
Info: Processing started: Mon Feb 5 00:57:25 2018
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off spw_fifo_ulight -c spw_fifo_ulight
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (115030): Assembler is generating device programming files
Info (11878): Hard Processor Subsystem configuration has not changed and a Preloader software update is not required
Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
Info: Peak virtual memory: 1044 megabytes
Info: Processing ended: Mon Feb 5 00:57:44 2018
Info: Elapsed time: 00:00:19
Info: Total CPU time (on all processors): 00:00:11
Error running this command: diff -w -U 5 "/tmp/lZhg5W" ""
diff: : No such file or directory