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-- Author: Jonny Doin, jdoin@opencores.org
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-- Author: Jonny Doin, jdoin@opencores.org, jonnydoin@gmail.com
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--
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--
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-- Create Date: 09:56:30 07/06/2011
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-- Create Date: 09:56:30 07/06/2011
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-- Module Name: grp_debouncer - RTL
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-- Module Name: grp_debouncer - RTL
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-- Project Name: basic functions
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-- Project Name: basic functions
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-- Target Devices: Spartan-6
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-- Target Devices: Spartan-6
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-- The number of registers inferred is: 3*N + (LOG(CNT_VAL)/LOG(2)) registers.
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-- The number of registers inferred is: 3*N + (LOG(CNT_VAL)/LOG(2)) registers.
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-- The number of LUTs inferred is roughly: ((4*N+2)/6)+2.
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-- The number of LUTs inferred is roughly: ((4*N+2)/6)+2.
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-- The slice distribution will vary, and depends on the control set restrictions and LUT-FF pairs resulting from map+p&r.
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-- The slice distribution will vary, and depends on the control set restrictions and LUT-FF pairs resulting from map+p&r.
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--
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--
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-- This design was originally targeted to a Spartan-6 platform, synthesized with XST and normal constraints.
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-- This design was originally targeted to a Spartan-6 platform, synthesized with XST and normal constraints.
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-- Verification in silicon was done on a Digilent Atlys board with a Spartan-6 FPGA @100MHz clk_i.
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-- The VHDL dialect used is VHDL'93, accepted largely by all synthesis tools.
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-- The VHDL dialect used is VHDL'93, accepted largely by all synthesis tools.
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--
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--
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------------------------------ COPYRIGHT NOTICE -----------------------------------------------------------------------
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------------------------------ COPYRIGHT NOTICE -----------------------------------------------------------------------
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--
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--
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--
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--
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-- Author(s): Jonny Doin, jdoin@opencores.org
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-- Author(s): Jonny Doin, jdoin@opencores.org, jonnydoin@gmail.com
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--
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--
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-- Copyright (C) 2011 Authors
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-- Copyright (C) 2011 Authors
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-- --------------------------
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-- --------------------------
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--
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--
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-- This source file may be used and distributed without restriction provided that this copyright statement is not
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-- This source file may be used and distributed without restriction provided that this copyright statement is not
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--
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--
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-- TODO
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-- TODO
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-- ====
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-- ====
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--
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--
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-- The circuit can easily be extended to have a signature of which inputs changed at the data out port.
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--
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--
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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