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SPI_MASTER_ATLYS
 
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This is a ISE 13.1 project to test the spi_master.vhd model in silicon.
This is a ISE 13.1 project to test the spi_master.vhd model in silicon.
 
 
The target board is a Digilent Atlys board (Spartan-6 @ 100MHz), and the circuit was tested at different SPI clock frequencies.
The target board is a Digilent Atlys FPGA board (Spartan-6 @ 100MHz), and the circuit was tested at different SPI clock frequencies.
 
 
See the scope screenshots in the spi_master_scope_photos.zip file for each SPI frequency tested.
See the scope screenshots in the spi_master_scope_photos.zip file for each SPI frequency tested.
 
 
This circuit also includes a very robust debouncing circuit to use with multiple inputs. The model, "grp_debouncer.vhd" is also published under a LGPL license.
This circuit also includes a very robust debouncing circuit to use with multiple inputs. The model, "grp_debouncer.vhd" is also published under a LGPL license.
 
 
The files are:
The files are:
 
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spi_master.vhd                  vhdl model for the spi_master interface
spi_master.vhd                  vhdl model for the spi_master interface
grp_debouncer.vhd               vhdl model for the switch debouncer
grp_debouncer.vhd               vhdl model for the switch debouncer
spi_master_atlys_top.vhd        vhdl model for the toplevel block to synthesize for the Atlys
spi_master_atlys_top.vhd        vhdl model for the toplevel block to synthesize for the Atlys
spi_master_atlys.xise           ISE 13.1 project file
spi_master_atlys.xise           ISE 13.1 project file
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In any case, thank you very much for testing this core.
In any case, thank you very much for testing this core.
 
 
 
 
Jonny Doin
Jonny Doin
jdoin@opencores.org
jdoin@opencores.org
 
 

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