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[/] [spi_master_slave/] [trunk/] [syn/] [spi_master.vhd] - Diff between revs 7 and 10

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Rev 7 Rev 10
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-- 2011/07/09   v1.00.0095  [JD]    changed all clocking scheme to use a single high-speed clock with clock enables to control lower 
-- 2011/07/09   v1.00.0095  [JD]    changed all clocking scheme to use a single high-speed clock with clock enables to control lower 
--                                  frequency sequential circuits, to preserve clocking resources and avoid path delay glitches.
--                                  frequency sequential circuits, to preserve clocking resources and avoid path delay glitches.
-- 2011/07/10   v1.00.0098  [JD]    implemented SCK clock divider circuit to generate spi clock directly from system clock.
-- 2011/07/10   v1.00.0098  [JD]    implemented SCK clock divider circuit to generate spi clock directly from system clock.
-- 2011/07/10   v1.10.0075  [JD]    verified spi_master_slave in silicon at 50MHz, 25MHz, 16.666MHz, 12.5MHz, 10MHz, 8.333MHz, 
-- 2011/07/10   v1.10.0075  [JD]    verified spi_master_slave in silicon at 50MHz, 25MHz, 16.666MHz, 12.5MHz, 10MHz, 8.333MHz, 
--                                  7.1428MHz, 6.25MHz, 1MHz and 500kHz. The core proved very robust at all tested frequencies.
--                                  7.1428MHz, 6.25MHz, 1MHz and 500kHz. The core proved very robust at all tested frequencies.
 
-- 2011/07/16   v1.11.0080  [JD]    verified both spi_master and spi_slave in loopback at 50MHz SPI clock.
--
--
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
--  TODO
--  TODO
--  ====
--  ====
--      > verify the receive interface in silicon, and determine the top usable frequency.
 
--
--
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_unsigned.all;
 
 
--================================================================================================================
--================================================================================================================
 
-- SYNTHESIS CONSIDERATIONS
 
-- ========================
-- There are several output ports that are used to simulate and verify the core operation. 
-- There are several output ports that are used to simulate and verify the core operation. 
-- Do not map any signals to the unused ports, and the synthesis tool will remove the related interfacing
-- Do not map any signals to the unused ports, and the synthesis tool will remove the related interfacing
-- circuitry. 
-- circuitry. 
-- The same is valid for the transmit and receive ports. If the receive ports are not mapped, the
-- The same is valid for the transmit and receive ports. If the receive ports are not mapped, the
-- synthesis tool will remove the receive logic from the generated circuitry.
-- synthesis tool will remove the receive logic from the generated circuitry.
Line 191... Line 193...
 
 
--================================================================================================================
--================================================================================================================
-- this architecture is a pipelined register-transfer description.
-- this architecture is a pipelined register-transfer description.
-- all signals are clocked at the rising edge of the system clock 'sclk_i'.
-- all signals are clocked at the rising edge of the system clock 'sclk_i'.
--================================================================================================================
--================================================================================================================
architecture rtl of spi_master is
architecture RTL of spi_master is
    -- core clocks, generated from 'sclk_i': initialized to differential values
    -- core clocks, generated from 'sclk_i': initialized to differential values
    signal core_clk : std_logic := '0';     -- continuous core clock, positive logic
    signal core_clk : std_logic := '0';     -- continuous core clock, positive logic
    signal core_n_clk : std_logic := '1';   -- continuous core clock, negative logic
    signal core_n_clk : std_logic := '1';   -- continuous core clock, negative logic
    signal core_ce : std_logic := '0';      -- core clock enable, positive logic
    signal core_ce : std_logic := '0';      -- core clock enable, positive logic
    signal core_n_ce : std_logic := '1';    -- core clock enable, negative logic
    signal core_n_ce : std_logic := '1';    -- core clock enable, negative logic
Line 373... Line 375...
    -- rx bit flop: capture rx bit after SAMPLE edge of sck
    -- rx bit flop: capture rx bit after SAMPLE edge of sck
    --
    --
    --  ATTENTION:  REMOVING THE FLIPFLOP (DIRECT CONNECTION) WE GET HIGHER PERFORMANCE DUE TO 
    --  ATTENTION:  REMOVING THE FLIPFLOP (DIRECT CONNECTION) WE GET HIGHER PERFORMANCE DUE TO 
    --              REDUCED DEMAND ON MISO SETUP TIME. 
    --              REDUCED DEMAND ON MISO SETUP TIME. 
    --
    --
    rx_bit_proc : process (sclk_i) is
    rx_bit_proc : process (sclk_i, spi_miso_i) is
    begin
    begin
        if sclk_i'event and sclk_i = '1' then
--        if sclk_i'event and sclk_i = '1' then
            if samp_ce = '1' then
--            if samp_ce = '1' then
                rx_bit_reg <= spi_miso_i;
                rx_bit_reg <= spi_miso_i;
            end if;
--            end if;
        end if;
--        end if;
    end process rx_bit_proc;
    end process rx_bit_proc;
 
 
    --=============================================================================================
    --=============================================================================================
    --  CROSS-CLOCK PIPELINE TRANSFER LOGIC
    --  CROSS-CLOCK PIPELINE TRANSFER LOGIC
    --=============================================================================================
    --=============================================================================================
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    core_clk_o_proc:    core_clk_o <= core_clk;
    core_clk_o_proc:    core_clk_o <= core_clk;
    core_n_clk_o_proc:  core_n_clk_o <= core_n_clk;
    core_n_clk_o_proc:  core_n_clk_o <= core_n_clk;
    core_ce_o_proc:     core_ce_o <= core_ce;
    core_ce_o_proc:     core_ce_o <= core_ce;
    core_n_ce_o_proc:   core_n_ce_o <= core_n_ce;
    core_n_ce_o_proc:   core_n_ce_o <= core_n_ce;
 
 
end architecture rtl;
end architecture RTL;
 
 
 
 
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