| Line 58... |
Line 58... |
--
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--
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--
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--
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-- PARALLEL READ INTERFACE
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-- PARALLEL READ INTERFACE
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-- =======================
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-- =======================
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-- An internal buffer is used to copy the internal shift register data to drive the 'do_o' port. When a complete word is received,
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-- An internal buffer is used to copy the internal shift register data to drive the 'do_o' port. When a complete word is received,
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-- the core shift register is transferred to the buffer, at the rising edge of the spi clock, 'spi_2x_clk_i'.
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-- the core shift register is transferred to the buffer, at the rising edge of the spi clock, 'spi_clk'.
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-- The signal 'do_valid_o' is set one 'spi_2x_clk_i' clock after, to directly drive a synchronous memory or fifo write enable.
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-- The signal 'do_valid_o' is set one 'spi_clk' clock after, to directly drive a synchronous memory or fifo write enable.
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-- 'do_valid_o' is synchronous to the parallel interface clock, and changes only on rising edges of 'pclk_i'.
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-- 'do_valid_o' is synchronous to the parallel interface clock, and changes only on rising edges of 'pclk_i'.
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-- When the interface is idle, data at the 'do_o' port holds the last word received.
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-- When the interface is idle, data at the 'do_o' port holds the last word received.
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--
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--
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-- PARALLEL READ SEQUENCE
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-- PARALLEL READ SEQUENCE
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-- ======================
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-- ======================
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-- ______ ______ ______ ______
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-- ______ ______ ______ ______
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-- spi_2x_clk_i bit1 \______/ bitN \______/bitN-1\______/bitN-2\__... -- spi 2x base clock
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-- spi_clk bit1 \______/ bitN \______/bitN-1\______/bitN-2\__... -- spi 2x base clock
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-- _ __ __ __ __ __ __ __ __
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-- _ __ __ __ __ __ __ __ __
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-- pclk_i \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \_... -- parallel interface clock (may be async to sclk_i)
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-- pclk_i \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \_... -- parallel interface clock (may be async to sclk_i)
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-- _____________ _____________________________________... -- 1) rx data is transferred to 'do_buffer_reg'
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-- _____________ _____________________________________... -- 1) rx data is transferred to 'do_buffer_reg'
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-- do_o ___old_data__X__________new_data___________________... -- after last rx bit, at rising 'spi_2x_clk_i'.
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-- do_o ___old_data__X__________new_data___________________... -- after last rx bit, at rising 'spi_clk'.
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-- ____________
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-- ____________
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-- do_valid_o ____________________________/ \_________... -- 2) 'do_valid_o' strobed for 2 'pclk_i' cycles
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-- do_valid_o ____________________________/ \_________... -- 2) 'do_valid_o' strobed for 2 'pclk_i' cycles
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-- -- on the 3rd 'pclk_i' rising edge.
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-- -- on the 3rd 'pclk_i' rising edge.
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--
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--
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--
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--
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| Line 167... |
Line 167... |
spi_ssel_o : out std_logic; -- spi bus slave select line
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spi_ssel_o : out std_logic; -- spi bus slave select line
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spi_sck_o : out std_logic; -- spi bus sck
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spi_sck_o : out std_logic; -- spi bus sck
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spi_mosi_o : out std_logic; -- spi bus mosi output
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spi_mosi_o : out std_logic; -- spi bus mosi output
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spi_miso_i : in std_logic := 'X'; -- spi bus spi_miso_i input
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spi_miso_i : in std_logic := 'X'; -- spi bus spi_miso_i input
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di_req_o : out std_logic; -- preload lookahead data request line
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di_req_o : out std_logic; -- preload lookahead data request line
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di_i : in std_logic_vector (N-1 downto 0) := (others => 'X'); -- parallel data in (clocked on rising spi_2x_clk_i after last bit)
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di_i : in std_logic_vector (N-1 downto 0) := (others => 'X'); -- parallel data in (clocked on rising spi_clk after last bit)
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wren_i : in std_logic := 'X'; -- user data write enable, starts transmission when interface is idle
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wren_i : in std_logic := 'X'; -- user data write enable, starts transmission when interface is idle
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do_valid_o : out std_logic; -- do_o data valid signal, valid during one spi_2x_clk_i rising edge.
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do_valid_o : out std_logic; -- do_o data valid signal, valid during one spi_clk rising edge.
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do_o : out std_logic_vector (N-1 downto 0); -- parallel output (clocked on rising spi_2x_clk_i after last bit)
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do_o : out std_logic_vector (N-1 downto 0); -- parallel output (clocked on rising spi_clk after last bit)
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--- debug ports: can be removed for the application circuit ---
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--- debug ports: can be removed for the application circuit ---
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do_transfer_o : out std_logic; -- debug: internal transfer driver
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do_transfer_o : out std_logic; -- debug: internal transfer driver
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wren_o : out std_logic; -- debug: internal state of the wren_i pulse stretcher
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wren_o : out std_logic; -- debug: internal state of the wren_i pulse stretcher
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wren_ack_o : out std_logic; -- debug: wren ack from state machine
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wren_ack_o : out std_logic; -- debug: wren ack from state machine
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rx_bit_reg_o : out std_logic; -- debug: internal rx bit
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rx_bit_reg_o : out std_logic; -- debug: internal rx bit
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| Line 187... |
Line 187... |
);
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);
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end spi_master;
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end spi_master;
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|
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--================================================================================================================
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--================================================================================================================
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-- this architecture is a pipelined register-transfer description.
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-- this architecture is a pipelined register-transfer description.
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-- all signals are clocked at the rising edge of the system clock 'spi_2x_clk_i'.
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-- all signals are clocked at the rising edge of the system clock 'sclk_i'.
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--================================================================================================================
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--================================================================================================================
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architecture rtl of spi_master is
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architecture rtl of spi_master is
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-- core clocks, generated from 'spi_2x_clk_i': initialized to differential values
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-- core clocks, generated from 'sclk_i': initialized to differential values
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signal core_clk : std_logic := '0'; -- continuous core clock, positive logic
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signal core_clk : std_logic := '0'; -- continuous core clock, positive logic
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signal core_n_clk : std_logic := '1'; -- continuous core clock, negative logic
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signal core_n_clk : std_logic := '1'; -- continuous core clock, negative logic
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signal core_ce : std_logic := '0'; -- core clock enable, positive logic
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signal core_ce : std_logic := '0'; -- core clock enable, positive logic
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signal core_n_ce : std_logic := '1'; -- core clock enable, negative logic
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signal core_n_ce : std_logic := '1'; -- core clock enable, negative logic
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-- spi bus clock, generated from the CPOL selected core clock polarity
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-- spi bus clock, generated from the CPOL selected core clock polarity
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| Line 293... |
Line 293... |
-- The clock enable phase is selected for serial input sampling, fsm clocking, and spi SCK output,
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-- The clock enable phase is selected for serial input sampling, fsm clocking, and spi SCK output,
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-- based on the configuration of CPOL and CPHA.
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-- based on the configuration of CPOL and CPHA.
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-- Each phase is selected so that all the registers can be clocked with a rising edge on all SPI
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-- Each phase is selected so that all the registers can be clocked with a rising edge on all SPI
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-- modes, by a single high-speed global clock, preserving clock resources.
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-- modes, by a single high-speed global clock, preserving clock resources.
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-----------------------------------------------------------------------------------------------
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-----------------------------------------------------------------------------------------------
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-- generate the core clock enables from the serial high-speed input clock
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-- generate the 2x spi base clock enable from the serial high-speed input clock
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spi_2x_ce_gen_proc: process (sclk_i) is
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spi_2x_ce_gen_proc: process (sclk_i) is
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variable clk_cnt : integer range SPI_2X_CLK_DIV-1 downto 0 := 0;
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variable clk_cnt : integer range SPI_2X_CLK_DIV-1 downto 0 := 0;
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begin
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begin
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if sclk_i'event and sclk_i = '1' then
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if sclk_i'event and sclk_i = '1' then
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if clk_cnt = SPI_2X_CLK_DIV-1 then
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if clk_cnt = SPI_2X_CLK_DIV-1 then
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| Line 308... |
Line 308... |
clk_cnt := clk_cnt + 1;
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clk_cnt := clk_cnt + 1;
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end if;
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end if;
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end if;
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end if;
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end process spi_2x_ce_gen_proc;
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end process spi_2x_ce_gen_proc;
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-----------------------------------------------------------------------------------------------
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-----------------------------------------------------------------------------------------------
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-- generate the core antiphase clocks and clock enables.
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-- generate the core antiphase clocks and clock enables from the 2x base CE.
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core_clock_gen_proc : process (sclk_i) is
|
core_clock_gen_proc : process (sclk_i) is
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begin
|
begin
|
if sclk_i'event and sclk_i = '1' then
|
if sclk_i'event and sclk_i = '1' then
|
if spi_2x_ce = '1' then
|
if spi_2x_ce = '1' then
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-- generate the 2 antiphase core clocks
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-- generate the 2 antiphase core clocks
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| Line 351... |
Line 351... |
if CPHA = '1' generate
|
if CPHA = '1' generate
|
begin
|
begin
|
samp_ce <= core_n_ce;
|
samp_ce <= core_n_ce;
|
end generate;
|
end generate;
|
-----------------------------------------------------------------------------------------------
|
-----------------------------------------------------------------------------------------------
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-- FSM clock generation: generate 'fsm_ce' from core_ce or core_n_ce depending on CPHA
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-- FSM clock enable generation: generate 'fsm_ce' from core_ce or core_n_ce depending on CPHA
|
fsm_ce_cpha_0_proc :
|
fsm_ce_cpha_0_proc :
|
if CPHA = '0' generate
|
if CPHA = '0' generate
|
begin
|
begin
|
fsm_ce <= core_n_ce; -- for CPHA=0, latch registers at rising edge of negative core clock enable
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fsm_ce <= core_n_ce; -- for CPHA=0, latch registers at rising edge of negative core clock enable
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end generate;
|
end generate;
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