| Line 34... |
Line 34... |
spi_ssel_o : out std_logic;
|
spi_ssel_o : out std_logic;
|
spi_sck_o : out std_logic;
|
spi_sck_o : out std_logic;
|
spi_mosi_o : out std_logic;
|
spi_mosi_o : out std_logic;
|
spi_miso_o : out std_logic;
|
spi_miso_o : out std_logic;
|
led_o : out std_logic_vector(7 downto 0);
|
led_o : out std_logic_vector(7 downto 0);
|
|
s_do_o : out std_logic_vector (7 downto 0);
|
|
m_do_o : out std_logic_vector (7 downto 0);
|
|
m_state_o : out std_logic_vector (3 downto 0);
|
|
s_state_o : out std_logic_vector (3 downto 0);
|
dbg_o : out std_logic_vector(11 downto 0)
|
dbg_o : out std_logic_vector(11 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
--=============================================================================================
|
--=============================================================================================
|
| Line 59... |
Line 63... |
signal spi_mosi : std_logic;
|
signal spi_mosi : std_logic;
|
signal spi_miso : std_logic;
|
signal spi_miso : std_logic;
|
-- debug output signals
|
-- debug output signals
|
signal leds : std_logic_vector (7 downto 0) := (others => '0');
|
signal leds : std_logic_vector (7 downto 0) := (others => '0');
|
signal dbg : std_logic_vector (11 downto 0) := (others => '0');
|
signal dbg : std_logic_vector (11 downto 0) := (others => '0');
|
-- debug ports
|
-- debug ports --
|
signal spi_do_s : std_logic_vector (7 downto 0) := (others => '0');
|
signal s_do_reg : std_logic_vector (7 downto 0);
|
signal spi_state_s : std_logic_vector (3 downto 0) := (others => '0');
|
signal m_do_reg : std_logic_vector (7 downto 0);
|
|
-- master signals mapped on dbg
|
|
signal wren_m : std_logic;
|
|
signal wr_ack_m : std_logic;
|
|
signal di_req_m : std_logic;
|
|
signal do_valid_m : std_logic;
|
|
signal master_state : std_logic_vector (3 downto 0);
|
|
-- slave signals mapped on dbg
|
|
signal wren_s : std_logic;
|
|
signal wr_ack_s : std_logic;
|
|
signal di_req_s : std_logic;
|
|
signal do_valid_s : std_logic;
|
|
signal slave_state : std_logic_vector (3 downto 0);
|
begin
|
begin
|
|
|
--=============================================================================================
|
--=============================================================================================
|
-- COMPONENT INSTANTIATIONS FOR THE CORES UNDER TEST
|
-- COMPONENT INSTANTIATIONS FOR THE CORES UNDER TEST
|
--=============================================================================================
|
--=============================================================================================
|
| Line 83... |
Line 99... |
spi_mosi_o => spi_mosi,
|
spi_mosi_o => spi_mosi,
|
spi_miso_o => spi_miso,
|
spi_miso_o => spi_miso,
|
sw_i => sw_data,
|
sw_i => sw_data,
|
btn_i => btn_data,
|
btn_i => btn_data,
|
led_o => leds,
|
led_o => leds,
|
|
m_state_o => master_state,
|
|
s_state_o => slave_state,
|
dbg_o => dbg
|
dbg_o => dbg
|
);
|
);
|
|
|
spi_do_s <= dbg(7 downto 0);
|
-- master signals mapped on dbg
|
spi_state_s <= dbg(11 downto 8);
|
wren_m <= dbg(11);
|
|
wr_ack_m <= dbg(10);
|
|
di_req_m <= dbg(9);
|
|
do_valid_m <= dbg(8);
|
|
-- slave signals mapped on dbg
|
|
wren_s <= dbg(7);
|
|
wr_ack_s <= dbg(6);
|
|
di_req_s <= dbg(5);
|
|
do_valid_s <= dbg(4);
|
|
|
|
|
--=============================================================================================
|
--=============================================================================================
|
-- CLOCK GENERATION
|
-- CLOCK GENERATION
|
--=============================================================================================
|
--=============================================================================================
|
gclk_proc: process is
|
gclk_proc: process is
|
| Line 107... |
Line 134... |
--=============================================================================================
|
--=============================================================================================
|
tb : process
|
tb : process
|
begin
|
begin
|
wait for 100 ns; -- wait until global set/reset completes
|
wait for 100 ns; -- wait until global set/reset completes
|
|
|
|
btn_data(btRESET) <= '1';
|
|
wait for 1 us;
|
|
btn_data(btRESET) <= '0';
|
|
wait for 900 ns;
|
|
|
sw_data <= X"5A";
|
sw_data <= X"5A";
|
btn_data(btRIGHT) <= '1';
|
|
|
|
wait; -- will wait forever
|
wait; -- will wait forever
|
end process tb;
|
end process tb;
|
-- End Test Bench
|
-- End Test Bench
|
END;
|
END;
|
