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[/] [spi_master_slave/] [trunk/] [syn/] [spi_master_atlys_test.vhd] - Diff between revs 13 and 20

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Rev 13 Rev 20
Line 99... Line 99...
        spi_mosi_o => spi_mosi,
        spi_mosi_o => spi_mosi,
        spi_miso_o => spi_miso,
        spi_miso_o => spi_miso,
        sw_i => sw_data,
        sw_i => sw_data,
        btn_i => btn_data,
        btn_i => btn_data,
        led_o => leds,
        led_o => leds,
 
        m_do_o => m_do_reg,
 
        s_do_o => s_do_reg,
        m_state_o => master_state,
        m_state_o => master_state,
        s_state_o => slave_state,
        s_state_o => slave_state,
        dbg_o => dbg
        dbg_o => dbg
        );
        );
 
 
    -- master signals mapped on dbg
    -- master signals mapped on dbg
    wren_m      <= dbg(11);
    wren_m      <= dbg(11);
    wr_ack_m    <= dbg(10);
    wr_ack_m    <= dbg(10);
    di_req_m    <= dbg(9);
    di_req_m    <= dbg(9);
    do_valid_m  <= dbg(8);
    do_valid_m  <= dbg(8);
 
 
    -- slave signals mapped on dbg
    -- slave signals mapped on dbg
    wren_s      <= dbg(7);
    wren_s      <= dbg(7);
    wr_ack_s    <= dbg(6);
    wr_ack_s    <= dbg(6);
    di_req_s    <= dbg(5);
    di_req_s    <= dbg(5);
    do_valid_s  <= dbg(4);
    do_valid_s  <= dbg(4);
Line 134... Line 137...
    --=============================================================================================
    --=============================================================================================
    tb : process
    tb : process
    begin
    begin
        wait for 100 ns; -- wait until global set/reset completes
        wait for 100 ns; -- wait until global set/reset completes
 
 
        btn_data(btRESET) <= '1';
        btn_data(btUP) <= '1';
        wait for 1 us;
        wait for 1 us;
        btn_data(btRESET) <= '0';
        btn_data(btUP) <= '0';
        wait for 900 ns;
        sw_data <= X"81";
 
        wait for 5 us;
        sw_data <= X"5A";
        sw_data <= X"C1";
 
        wait for 5 us;
        wait; -- will wait forever
        sw_data <= X"C9";
 
        wait for 5 us;
 
        sw_data <= X"55";
 
        wait for 5 us;
 
        assert false report "End Simulation" severity failure; -- stop simulation
    end process tb;
    end process tb;
    --  End Test Bench 
    --  End Test Bench 
END;
END;
 
 
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