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[/] [spi_master_slave/] [trunk/] [syn/] [spi_master_atlys_test.vhd] - Diff between revs 13 and 20
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| Rev 13 |
Rev 20 |
| Line 99... |
Line 99... |
spi_mosi_o => spi_mosi,
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spi_mosi_o => spi_mosi,
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spi_miso_o => spi_miso,
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spi_miso_o => spi_miso,
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sw_i => sw_data,
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sw_i => sw_data,
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btn_i => btn_data,
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btn_i => btn_data,
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led_o => leds,
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led_o => leds,
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m_do_o => m_do_reg,
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s_do_o => s_do_reg,
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m_state_o => master_state,
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m_state_o => master_state,
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s_state_o => slave_state,
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s_state_o => slave_state,
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dbg_o => dbg
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dbg_o => dbg
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);
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);
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-- master signals mapped on dbg
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-- master signals mapped on dbg
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wren_m <= dbg(11);
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wren_m <= dbg(11);
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wr_ack_m <= dbg(10);
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wr_ack_m <= dbg(10);
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di_req_m <= dbg(9);
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di_req_m <= dbg(9);
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do_valid_m <= dbg(8);
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do_valid_m <= dbg(8);
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|
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-- slave signals mapped on dbg
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-- slave signals mapped on dbg
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wren_s <= dbg(7);
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wren_s <= dbg(7);
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wr_ack_s <= dbg(6);
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wr_ack_s <= dbg(6);
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di_req_s <= dbg(5);
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di_req_s <= dbg(5);
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do_valid_s <= dbg(4);
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do_valid_s <= dbg(4);
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| Line 134... |
Line 137... |
--=============================================================================================
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--=============================================================================================
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tb : process
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tb : process
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begin
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begin
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wait for 100 ns; -- wait until global set/reset completes
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wait for 100 ns; -- wait until global set/reset completes
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btn_data(btRESET) <= '1';
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btn_data(btUP) <= '1';
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wait for 1 us;
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wait for 1 us;
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btn_data(btRESET) <= '0';
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btn_data(btUP) <= '0';
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wait for 900 ns;
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sw_data <= X"81";
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wait for 5 us;
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sw_data <= X"5A";
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sw_data <= X"C1";
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wait for 5 us;
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wait; -- will wait forever
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sw_data <= X"C9";
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wait for 5 us;
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sw_data <= X"55";
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wait for 5 us;
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assert false report "End Simulation" severity failure; -- stop simulation
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end process tb;
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end process tb;
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-- End Test Bench
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-- End Test Bench
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END;
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END;
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No newline at end of file
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No newline at end of file
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