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[/] [spi_master_slave/] [trunk/] [syn/] [spi_master_atlys_test.vhd] - Diff between revs 22 and 24

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Line 11... Line 11...
 
 
    --=============================================================================================
    --=============================================================================================
    -- Constants
    -- Constants
    --=============================================================================================
    --=============================================================================================
    -- clock period
    -- clock period
    constant CLK_PERIOD : time := 10 ns;
    constant SCLK_PERIOD : time := 11 ns;           -- serial high speed clock
 
    constant PCLK_PERIOD : time := 10 ns;           -- parallel high-speed clock
 
 
    -- button definitions
    -- button definitions
    constant btRESET    : integer := 0;             -- these are constants to use as btn_i(x)
    constant btRESET    : integer := 0;             -- these are constants to use as btn_i(x)
    constant btUP       : integer := 1;
    constant btUP       : integer := 1;
    constant btLEFT     : integer := 2;
    constant btLEFT     : integer := 2;
Line 26... Line 27...
    --=============================================================================================
    --=============================================================================================
    -- COMPONENT DECLARATIONS
    -- COMPONENT DECLARATIONS
    --=============================================================================================
    --=============================================================================================
    component spi_master_atlys_top
    component spi_master_atlys_top
    port(
    port(
        gclk_i : in std_logic;
        sclk_i : in std_logic;
 
        pclk_i : in std_logic;
        sw_i : in std_logic_vector(7 downto 0);
        sw_i : in std_logic_vector(7 downto 0);
        btn_i : in std_logic_vector(5 downto 0);
        btn_i : in std_logic_vector(5 downto 0);
        spi_ssel_o : out std_logic;
        spi_ssel_o : out std_logic;
        spi_sck_o : out std_logic;
        spi_sck_o : out std_logic;
        spi_mosi_o : out std_logic;
        spi_mosi_o : out std_logic;
Line 51... Line 53...
    --=============================================================================================
    --=============================================================================================
    -- Signals for internal operation
    -- Signals for internal operation
    --=============================================================================================
    --=============================================================================================
    --- clock signals ---
    --- clock signals ---
    signal sysclk           : std_logic := '0';                                 -- 100MHz clock
    signal sysclk           : std_logic := '0';                                 -- 100MHz clock
 
    signal pclk             : std_logic := '0';                                 -- 100MHz clock
    --- switch debouncer signals ---
    --- switch debouncer signals ---
    signal sw_data          : std_logic_vector (7 downto 0) := (others => '0'); -- switch data
    signal sw_data          : std_logic_vector (7 downto 0) := (others => '0'); -- switch data
    --- pushbutton debouncer signals ---
    --- pushbutton debouncer signals ---
    signal btn_data         : std_logic_vector (5 downto 0) := (others => '0'); -- pushbuttons
    signal btn_data         : std_logic_vector (5 downto 0) := (others => '0'); -- pushbuttons
    --- spi port signals ---
    --- spi port signals ---
Line 92... Line 95...
    --      connects to 8 board LEDs
    --      connects to 8 board LEDs
    --      connects to 12 debug pins
    --      connects to 12 debug pins
    --      set debounce time to 2 us to save simulation time
    --      set debounce time to 2 us to save simulation time
        Inst_spi_master_atlys_top: spi_master_atlys_top
        Inst_spi_master_atlys_top: spi_master_atlys_top
        port map(
        port map(
            gclk_i => sysclk,
            sclk_i => sysclk,
 
            pclk_i => pclk,
            spi_ssel_o => spi_ssel,
            spi_ssel_o => spi_ssel,
            spi_sck_o => spi_sck,
            spi_sck_o => spi_sck,
            spi_mosi_o => spi_mosi,
            spi_mosi_o => spi_mosi,
            spi_miso_o => spi_miso,
            spi_miso_o => spi_miso,
            sw_i => sw_data,
            sw_i => sw_data,
Line 123... Line 127...
 
 
 
 
    --=============================================================================================
    --=============================================================================================
    -- CLOCK GENERATION
    -- CLOCK GENERATION
    --=============================================================================================
    --=============================================================================================
    gclk_proc: process is
    sysclk_proc: process is
    begin
    begin
        loop
        loop
            sysclk <= not sysclk;
            sysclk <= not sysclk;
            wait for CLK_PERIOD / 2;
            wait for SCLK_PERIOD / 2;
        end loop;
        end loop;
    end process gclk_proc;
    end process sysclk_proc;
 
 
 
    pclk_proc: process is
 
    begin
 
        loop
 
            pclk <= not pclk;
 
            wait for PCLK_PERIOD / 2;
 
        end loop;
 
    end process pclk_proc;
 
 
    --=============================================================================================
    --=============================================================================================
    -- TEST BENCH STIMULI
    -- TEST BENCH STIMULI
    --=============================================================================================
    --=============================================================================================
    tb : process
    tb : process
Line 149... Line 161...
        wait for 5 us;
        wait for 5 us;
        sw_data <= X"C9";
        sw_data <= X"C9";
        wait for 5 us;
        wait for 5 us;
        sw_data <= X"55";
        sw_data <= X"55";
        wait for 5 us;
        wait for 5 us;
 
        sw_data <= X"AA";
 
        wait for 5 us;
 
        sw_data <= X"1e";
 
        wait for 5 us;
 
        sw_data <= X"79";
 
        wait for 5 us;
 
        sw_data <= X"40";
 
        wait for 5 us;
        assert false report "End Simulation" severity failure; -- stop simulation
        assert false report "End Simulation" severity failure; -- stop simulation
    end process tb;
    end process tb;
    --  End Test Bench 
    --  End Test Bench 
END;
END;
 
 
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