| Line 11... |
Line 11... |
|
|
--=============================================================================================
|
--=============================================================================================
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-- Constants
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-- Constants
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--=============================================================================================
|
--=============================================================================================
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-- clock period
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-- clock period
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constant CLK_PERIOD : time := 10 ns;
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constant SCLK_PERIOD : time := 11 ns; -- serial high speed clock
|
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constant PCLK_PERIOD : time := 10 ns; -- parallel high-speed clock
|
|
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-- button definitions
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-- button definitions
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constant btRESET : integer := 0; -- these are constants to use as btn_i(x)
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constant btRESET : integer := 0; -- these are constants to use as btn_i(x)
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constant btUP : integer := 1;
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constant btUP : integer := 1;
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constant btLEFT : integer := 2;
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constant btLEFT : integer := 2;
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| Line 26... |
Line 27... |
--=============================================================================================
|
--=============================================================================================
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-- COMPONENT DECLARATIONS
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-- COMPONENT DECLARATIONS
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--=============================================================================================
|
--=============================================================================================
|
component spi_master_atlys_top
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component spi_master_atlys_top
|
port(
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port(
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gclk_i : in std_logic;
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sclk_i : in std_logic;
|
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pclk_i : in std_logic;
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sw_i : in std_logic_vector(7 downto 0);
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sw_i : in std_logic_vector(7 downto 0);
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btn_i : in std_logic_vector(5 downto 0);
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btn_i : in std_logic_vector(5 downto 0);
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spi_ssel_o : out std_logic;
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spi_ssel_o : out std_logic;
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spi_sck_o : out std_logic;
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spi_sck_o : out std_logic;
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spi_mosi_o : out std_logic;
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spi_mosi_o : out std_logic;
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| Line 51... |
Line 53... |
--=============================================================================================
|
--=============================================================================================
|
-- Signals for internal operation
|
-- Signals for internal operation
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--=============================================================================================
|
--=============================================================================================
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--- clock signals ---
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--- clock signals ---
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signal sysclk : std_logic := '0'; -- 100MHz clock
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signal sysclk : std_logic := '0'; -- 100MHz clock
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signal pclk : std_logic := '0'; -- 100MHz clock
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--- switch debouncer signals ---
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--- switch debouncer signals ---
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signal sw_data : std_logic_vector (7 downto 0) := (others => '0'); -- switch data
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signal sw_data : std_logic_vector (7 downto 0) := (others => '0'); -- switch data
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--- pushbutton debouncer signals ---
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--- pushbutton debouncer signals ---
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signal btn_data : std_logic_vector (5 downto 0) := (others => '0'); -- pushbuttons
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signal btn_data : std_logic_vector (5 downto 0) := (others => '0'); -- pushbuttons
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--- spi port signals ---
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--- spi port signals ---
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| Line 92... |
Line 95... |
-- connects to 8 board LEDs
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-- connects to 8 board LEDs
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-- connects to 12 debug pins
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-- connects to 12 debug pins
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-- set debounce time to 2 us to save simulation time
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-- set debounce time to 2 us to save simulation time
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Inst_spi_master_atlys_top: spi_master_atlys_top
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Inst_spi_master_atlys_top: spi_master_atlys_top
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port map(
|
port map(
|
gclk_i => sysclk,
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sclk_i => sysclk,
|
|
pclk_i => pclk,
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spi_ssel_o => spi_ssel,
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spi_ssel_o => spi_ssel,
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spi_sck_o => spi_sck,
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spi_sck_o => spi_sck,
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spi_mosi_o => spi_mosi,
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spi_mosi_o => spi_mosi,
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spi_miso_o => spi_miso,
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spi_miso_o => spi_miso,
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sw_i => sw_data,
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sw_i => sw_data,
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| Line 123... |
Line 127... |
|
|
|
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--=============================================================================================
|
--=============================================================================================
|
-- CLOCK GENERATION
|
-- CLOCK GENERATION
|
--=============================================================================================
|
--=============================================================================================
|
gclk_proc: process is
|
sysclk_proc: process is
|
begin
|
begin
|
loop
|
loop
|
sysclk <= not sysclk;
|
sysclk <= not sysclk;
|
wait for CLK_PERIOD / 2;
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wait for SCLK_PERIOD / 2;
|
end loop;
|
end loop;
|
end process gclk_proc;
|
end process sysclk_proc;
|
|
|
|
pclk_proc: process is
|
|
begin
|
|
loop
|
|
pclk <= not pclk;
|
|
wait for PCLK_PERIOD / 2;
|
|
end loop;
|
|
end process pclk_proc;
|
|
|
--=============================================================================================
|
--=============================================================================================
|
-- TEST BENCH STIMULI
|
-- TEST BENCH STIMULI
|
--=============================================================================================
|
--=============================================================================================
|
tb : process
|
tb : process
|
| Line 149... |
Line 161... |
wait for 5 us;
|
wait for 5 us;
|
sw_data <= X"C9";
|
sw_data <= X"C9";
|
wait for 5 us;
|
wait for 5 us;
|
sw_data <= X"55";
|
sw_data <= X"55";
|
wait for 5 us;
|
wait for 5 us;
|
|
sw_data <= X"AA";
|
|
wait for 5 us;
|
|
sw_data <= X"1e";
|
|
wait for 5 us;
|
|
sw_data <= X"79";
|
|
wait for 5 us;
|
|
sw_data <= X"40";
|
|
wait for 5 us;
|
assert false report "End Simulation" severity failure; -- stop simulation
|
assert false report "End Simulation" severity failure; -- stop simulation
|
end process tb;
|
end process tb;
|
-- End Test Bench
|
-- End Test Bench
|
END;
|
END;
|
|
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No newline at end of file
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No newline at end of file
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