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[/] [spi_master_slave/] [trunk/] [syn/] [spi_master_atlys_top.par] - Diff between revs 20 and 22

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Rev 20 Rev 22
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Release 13.1 par O.40d (nt)
Release 13.1 par O.40d (nt)
Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
 
 
DEVELOP-W7::  Wed Aug 10 22:56:51 2011
DEVELOP-W7::  Mon Aug 29 00:08:38 2011
 
 
par -w -intstyle ise -ol high -xe n -mt 4 spi_master_atlys_top_map.ncd
par -w -intstyle ise -ol high -xe n -mt 4 spi_master_atlys_top_map.ncd
spi_master_atlys_top.ncd spi_master_atlys_top.pcf
spi_master_atlys_top.ncd spi_master_atlys_top.pcf
 
 
 
 
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Device Utilization Summary:
Device Utilization Summary:
 
 
Slice Logic Utilization:
Slice Logic Utilization:
  Number of Slice Registers:                   209 out of  54,576    1%
  Number of Slice Registers:                   224 out of  54,576    1%
    Number used as Flip Flops:                 209
    Number used as Flip Flops:                 224
    Number used as Latches:                      0
    Number used as Latches:                      0
    Number used as Latch-thrus:                  0
    Number used as Latch-thrus:                  0
    Number used as AND/OR logics:                0
    Number used as AND/OR logics:                0
  Number of Slice LUTs:                        145 out of  27,288    1%
  Number of Slice LUTs:                        177 out of  27,288    1%
    Number used as logic:                      127 out of  27,288    1%
    Number used as logic:                      167 out of  27,288    1%
      Number using O6 output only:              75
      Number using O6 output only:             112
      Number using O5 output only:              13
      Number using O5 output only:              28
      Number using O5 and O6:                   39
      Number using O5 and O6:                   27
      Number used as ROM:                        0
      Number used as ROM:                        0
    Number used as Memory:                       4 out of   6,408    1%
    Number used as Memory:                       4 out of   6,408    1%
      Number used as Dual Port RAM:              0
      Number used as Dual Port RAM:              0
      Number used as Single Port RAM:            0
      Number used as Single Port RAM:            0
      Number used as Shift Register:             4
      Number used as Shift Register:             4
        Number using O6 output only:             4
        Number using O6 output only:             4
        Number using O5 output only:             0
        Number using O5 output only:             0
        Number using O5 and O6:                  0
        Number using O5 and O6:                  0
    Number used exclusively as route-thrus:     14
    Number used exclusively as route-thrus:      6
      Number with same-slice register load:     12
      Number with same-slice register load:      4
      Number with same-slice carry load:         2
      Number with same-slice carry load:         2
      Number with other load:                    0
      Number with other load:                    0
 
 
Slice Logic Distribution:
Slice Logic Distribution:
  Number of occupied Slices:                    91 out of   6,822    1%
  Number of occupied Slices:                   102 out of   6,822    1%
  Number of LUT Flip Flop pairs used:          225
  Number of LUT Flip Flop pairs used:          272
    Number with an unused Flip Flop:            49 out of     225   21%
    Number with an unused Flip Flop:            64 out of     272   23%
    Number with an unused LUT:                  80 out of     225   35%
    Number with an unused LUT:                  95 out of     272   34%
    Number of fully used LUT-FF pairs:          96 out of     225   42%
    Number of fully used LUT-FF pairs:         113 out of     272   41%
    Number of slice register sites lost
    Number of slice register sites lost
      to control set restrictions:               0 out of  54,576    0%
      to control set restrictions:               0 out of  54,576    0%
 
 
  A LUT Flip Flop pair for this architecture represents one LUT paired with
  A LUT Flip Flop pair for this architecture represents one LUT paired with
  one Flip Flop within a slice.  A control set is a unique combination of
  one Flip Flop within a slice.  A control set is a unique combination of
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  The Slice Logic Distribution report is not meaningful if the design is
  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.
  over-mapped for a non-slice resource or if Placement fails.
 
 
IO Utilization:
IO Utilization:
  Number of bonded IOBs:                        63 out of     218   28%
  Number of bonded IOBs:                        63 out of     218   28%
    Number of LOCed IOBs:                       43 out of      63   68%
    Number of LOCed IOBs:                       47 out of      63   74%
 
 
Specific Feature Utilization:
Specific Feature Utilization:
  Number of RAMB16BWERs:                         0 out of     116    0%
  Number of RAMB16BWERs:                         0 out of     116    0%
  Number of RAMB8BWERs:                          0 out of     232    0%
  Number of RAMB8BWERs:                          0 out of     232    0%
  Number of BUFIO2/BUFIO2_2CLKs:                 0 out of      32    0%
  Number of BUFIO2/BUFIO2_2CLKs:                 0 out of      32    0%
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Finished initial Timing Analysis.  REAL time: 4 secs
Finished initial Timing Analysis.  REAL time: 4 secs
 
 
Starting Router
Starting Router
 
 
 
 
Phase  1  : 910 unrouted;      REAL time: 5 secs
Phase  1  : 1133 unrouted;      REAL time: 5 secs
 
 
Phase  2  : 760 unrouted;      REAL time: 6 secs
Phase  2  : 972 unrouted;      REAL time: 6 secs
 
 
Phase  3  : 207 unrouted;      REAL time: 7 secs
Phase  3  : 282 unrouted;      REAL time: 7 secs
 
 
Phase  4  : 207 unrouted; (Par is working to improve performance)     REAL time: 9 secs
Phase  4  : 282 unrouted; (Par is working to improve performance)     REAL time: 9 secs
 
 
Updating file: spi_master_atlys_top.ncd with current fully routed design.
Updating file: spi_master_atlys_top.ncd with current fully routed design.
 
 
Phase  5  : 0 unrouted; (Par is working to improve performance)     REAL time: 9 secs
Phase  5  : 0 unrouted; (Par is working to improve performance)     REAL time: 9 secs
 
 
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----------------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------------
  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing
  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing
                                            |             |    Slack   | Achievable | Errors |    Score
                                            |             |    Slack   | Achievable | Errors |    Score
----------------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------------
  Autotimespec constraint for clock net gcl | SETUP       |         N/A|     5.299ns|     N/A|           0
  Autotimespec constraint for clock net gcl | SETUP       |         N/A|     4.888ns|     N/A|           0
  k_i_BUFGP                                 | HOLD        |     0.388ns|            |       0|           0
  k_i_BUFGP                                 | HOLD        |     0.378ns|            |       0|           0
----------------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------------
  Autotimespec constraint for clock net Ins | SETUP       |         N/A|     5.052ns|     N/A|           0
  Autotimespec constraint for clock net Ins | SETUP       |         N/A|     3.948ns|     N/A|           0
  t_spi_master_port/spi_clk_reg_BUFG        | HOLD        |     0.497ns|            |       0|           0
  t_spi_master_port/spi_clk_reg_BUFG        | HOLD        |     0.459ns|            |       0|           0
----------------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------------
 
 
 
 
All constraints were met.
All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
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All signals are completely routed.
All signals are completely routed.
 
 
Total REAL time to PAR completion: 10 secs
Total REAL time to PAR completion: 10 secs
Total CPU time to PAR completion: 10 secs
Total CPU time to PAR completion: 10 secs
 
 
Peak Memory Usage:  269 MB
Peak Memory Usage:  264 MB
 
 
Placer: Placement generated during map.
Placer: Placement generated during map.
Routing: Completed - No errors found.
Routing: Completed - No errors found.
 
 
Number of error messages: 0
Number of error messages: 0

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