Release 13.1 par O.40d (nt)
|
Release 13.1 par O.40d (nt)
|
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
|
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
|
|
|
DEVELOP-W7:: Wed Aug 10 22:56:51 2011
|
DEVELOP-W7:: Mon Aug 29 00:08:38 2011
|
|
|
par -w -intstyle ise -ol high -xe n -mt 4 spi_master_atlys_top_map.ncd
|
par -w -intstyle ise -ol high -xe n -mt 4 spi_master_atlys_top_map.ncd
|
spi_master_atlys_top.ncd spi_master_atlys_top.pcf
|
spi_master_atlys_top.ncd spi_master_atlys_top.pcf
|
|
|
|
|
Constraints file: spi_master_atlys_top.pcf.
|
Constraints file: spi_master_atlys_top.pcf.
|
Loading device for application Rf_Device from file '6slx45.nph' in environment C:\Xilinx\13.1\ISE_DS\ISE\.
|
Loading device for application Rf_Device from file '6slx45.nph' in environment C:\Xilinx\13.1\ISE_DS\ISE\.
|
"spi_master_atlys_top" is an NCD, version 3.2, device xc6slx45, package csg324, speed -2
|
"spi_master_atlys_top" is an NCD, version 3.2, device xc6slx45, package csg324, speed -2
|
|
|
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
|
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
|
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
|
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
|
|
|
INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
|
INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
|
-x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
|
-x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
|
internal clocks in this design. Because there are not defined timing requirements, a timing score will not be
|
internal clocks in this design. Because there are not defined timing requirements, a timing score will not be
|
reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock.
|
reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock.
|
Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high".
|
Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high".
|
|
|
Device speed data version: "PRODUCTION 1.18 2011-04-07".
|
Device speed data version: "PRODUCTION 1.18 2011-04-07".
|
|
|
|
|
|
|
Device Utilization Summary:
|
Device Utilization Summary:
|
|
|
Slice Logic Utilization:
|
Slice Logic Utilization:
|
Number of Slice Registers: 209 out of 54,576 1%
|
Number of Slice Registers: 224 out of 54,576 1%
|
Number used as Flip Flops: 209
|
Number used as Flip Flops: 224
|
Number used as Latches: 0
|
Number used as Latches: 0
|
Number used as Latch-thrus: 0
|
Number used as Latch-thrus: 0
|
Number used as AND/OR logics: 0
|
Number used as AND/OR logics: 0
|
Number of Slice LUTs: 145 out of 27,288 1%
|
Number of Slice LUTs: 177 out of 27,288 1%
|
Number used as logic: 127 out of 27,288 1%
|
Number used as logic: 167 out of 27,288 1%
|
Number using O6 output only: 75
|
Number using O6 output only: 112
|
Number using O5 output only: 13
|
Number using O5 output only: 28
|
Number using O5 and O6: 39
|
Number using O5 and O6: 27
|
Number used as ROM: 0
|
Number used as ROM: 0
|
Number used as Memory: 4 out of 6,408 1%
|
Number used as Memory: 4 out of 6,408 1%
|
Number used as Dual Port RAM: 0
|
Number used as Dual Port RAM: 0
|
Number used as Single Port RAM: 0
|
Number used as Single Port RAM: 0
|
Number used as Shift Register: 4
|
Number used as Shift Register: 4
|
Number using O6 output only: 4
|
Number using O6 output only: 4
|
Number using O5 output only: 0
|
Number using O5 output only: 0
|
Number using O5 and O6: 0
|
Number using O5 and O6: 0
|
Number used exclusively as route-thrus: 14
|
Number used exclusively as route-thrus: 6
|
Number with same-slice register load: 12
|
Number with same-slice register load: 4
|
Number with same-slice carry load: 2
|
Number with same-slice carry load: 2
|
Number with other load: 0
|
Number with other load: 0
|
|
|
Slice Logic Distribution:
|
Slice Logic Distribution:
|
Number of occupied Slices: 91 out of 6,822 1%
|
Number of occupied Slices: 102 out of 6,822 1%
|
Number of LUT Flip Flop pairs used: 225
|
Number of LUT Flip Flop pairs used: 272
|
Number with an unused Flip Flop: 49 out of 225 21%
|
Number with an unused Flip Flop: 64 out of 272 23%
|
Number with an unused LUT: 80 out of 225 35%
|
Number with an unused LUT: 95 out of 272 34%
|
Number of fully used LUT-FF pairs: 96 out of 225 42%
|
Number of fully used LUT-FF pairs: 113 out of 272 41%
|
Number of slice register sites lost
|
Number of slice register sites lost
|
to control set restrictions: 0 out of 54,576 0%
|
to control set restrictions: 0 out of 54,576 0%
|
|
|
A LUT Flip Flop pair for this architecture represents one LUT paired with
|
A LUT Flip Flop pair for this architecture represents one LUT paired with
|
one Flip Flop within a slice. A control set is a unique combination of
|
one Flip Flop within a slice. A control set is a unique combination of
|
clock, reset, set, and enable signals for a registered element.
|
clock, reset, set, and enable signals for a registered element.
|
The Slice Logic Distribution report is not meaningful if the design is
|
The Slice Logic Distribution report is not meaningful if the design is
|
over-mapped for a non-slice resource or if Placement fails.
|
over-mapped for a non-slice resource or if Placement fails.
|
|
|
IO Utilization:
|
IO Utilization:
|
Number of bonded IOBs: 63 out of 218 28%
|
Number of bonded IOBs: 63 out of 218 28%
|
Number of LOCed IOBs: 43 out of 63 68%
|
Number of LOCed IOBs: 47 out of 63 74%
|
|
|
Specific Feature Utilization:
|
Specific Feature Utilization:
|
Number of RAMB16BWERs: 0 out of 116 0%
|
Number of RAMB16BWERs: 0 out of 116 0%
|
Number of RAMB8BWERs: 0 out of 232 0%
|
Number of RAMB8BWERs: 0 out of 232 0%
|
Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
|
Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
|
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
|
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
|
Number of BUFG/BUFGMUXs: 2 out of 16 12%
|
Number of BUFG/BUFGMUXs: 2 out of 16 12%
|
Number used as BUFGs: 2
|
Number used as BUFGs: 2
|
Number used as BUFGMUX: 0
|
Number used as BUFGMUX: 0
|
Number of DCM/DCM_CLKGENs: 0 out of 8 0%
|
Number of DCM/DCM_CLKGENs: 0 out of 8 0%
|
Number of ILOGIC2/ISERDES2s: 0 out of 376 0%
|
Number of ILOGIC2/ISERDES2s: 0 out of 376 0%
|
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 376 0%
|
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 376 0%
|
Number of OLOGIC2/OSERDES2s: 0 out of 376 0%
|
Number of OLOGIC2/OSERDES2s: 0 out of 376 0%
|
Number of BSCANs: 0 out of 4 0%
|
Number of BSCANs: 0 out of 4 0%
|
Number of BUFHs: 0 out of 256 0%
|
Number of BUFHs: 0 out of 256 0%
|
Number of BUFPLLs: 0 out of 8 0%
|
Number of BUFPLLs: 0 out of 8 0%
|
Number of BUFPLL_MCBs: 0 out of 4 0%
|
Number of BUFPLL_MCBs: 0 out of 4 0%
|
Number of DSP48A1s: 0 out of 58 0%
|
Number of DSP48A1s: 0 out of 58 0%
|
Number of ICAPs: 0 out of 1 0%
|
Number of ICAPs: 0 out of 1 0%
|
Number of MCBs: 0 out of 2 0%
|
Number of MCBs: 0 out of 2 0%
|
Number of PCILOGICSEs: 0 out of 2 0%
|
Number of PCILOGICSEs: 0 out of 2 0%
|
Number of PLL_ADVs: 0 out of 4 0%
|
Number of PLL_ADVs: 0 out of 4 0%
|
Number of PMVs: 0 out of 1 0%
|
Number of PMVs: 0 out of 1 0%
|
Number of STARTUPs: 0 out of 1 0%
|
Number of STARTUPs: 0 out of 1 0%
|
Number of SUSPEND_SYNCs: 0 out of 1 0%
|
Number of SUSPEND_SYNCs: 0 out of 1 0%
|
|
|
|
|
Overall effort level (-ol): High
|
Overall effort level (-ol): High
|
Router effort level (-rl): High
|
Router effort level (-rl): High
|
|
|
WARNING:Par:545 - Multi-threading ("-mt" option) is not supported for the Performance Evaluation Mode. PAR will use only one processor.
|
WARNING:Par:545 - Multi-threading ("-mt" option) is not supported for the Performance Evaluation Mode. PAR will use only one processor.
|
|
|
Starting initial Timing Analysis. REAL time: 4 secs
|
Starting initial Timing Analysis. REAL time: 4 secs
|
Finished initial Timing Analysis. REAL time: 4 secs
|
Finished initial Timing Analysis. REAL time: 4 secs
|
|
|
Starting Router
|
Starting Router
|
|
|
|
|
Phase 1 : 910 unrouted; REAL time: 5 secs
|
Phase 1 : 1133 unrouted; REAL time: 5 secs
|
|
|
Phase 2 : 760 unrouted; REAL time: 6 secs
|
Phase 2 : 972 unrouted; REAL time: 6 secs
|
|
|
Phase 3 : 207 unrouted; REAL time: 7 secs
|
Phase 3 : 282 unrouted; REAL time: 7 secs
|
|
|
Phase 4 : 207 unrouted; (Par is working to improve performance) REAL time: 9 secs
|
Phase 4 : 282 unrouted; (Par is working to improve performance) REAL time: 9 secs
|
|
|
Updating file: spi_master_atlys_top.ncd with current fully routed design.
|
Updating file: spi_master_atlys_top.ncd with current fully routed design.
|
|
|
Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 9 secs
|
Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 9 secs
|
|
|
Phase 6 : 0 unrouted; (Par is working to improve performance) REAL time: 9 secs
|
Phase 6 : 0 unrouted; (Par is working to improve performance) REAL time: 9 secs
|
|
|
Phase 7 : 0 unrouted; (Par is working to improve performance) REAL time: 9 secs
|
Phase 7 : 0 unrouted; (Par is working to improve performance) REAL time: 9 secs
|
|
|
Phase 8 : 0 unrouted; (Par is working to improve performance) REAL time: 9 secs
|
Phase 8 : 0 unrouted; (Par is working to improve performance) REAL time: 9 secs
|
|
|
Phase 9 : 0 unrouted; (Par is working to improve performance) REAL time: 9 secs
|
Phase 9 : 0 unrouted; (Par is working to improve performance) REAL time: 9 secs
|
|
|
Phase 10 : 0 unrouted; (Par is working to improve performance) REAL time: 9 secs
|
Phase 10 : 0 unrouted; (Par is working to improve performance) REAL time: 9 secs
|
Total REAL time to Router completion: 9 secs
|
Total REAL time to Router completion: 9 secs
|
Total CPU time to Router completion: 9 secs
|
Total CPU time to Router completion: 9 secs
|
|
|
Partition Implementation Status
|
Partition Implementation Status
|
-------------------------------
|
-------------------------------
|
|
|
No Partitions were found in this design.
|
No Partitions were found in this design.
|
|
|
-------------------------------
|
-------------------------------
|
|
|
Generating "PAR" statistics.
|
Generating "PAR" statistics.
|
INFO:Par:459 - The Clock Report is not displayed in the non timing-driven mode.
|
INFO:Par:459 - The Clock Report is not displayed in the non timing-driven mode.
|
Timing Score: 0 (Setup: 0, Hold: 0)
|
Timing Score: 0 (Setup: 0, Hold: 0)
|
|
|
Asterisk (*) preceding a constraint indicates it was not met.
|
Asterisk (*) preceding a constraint indicates it was not met.
|
This may be due to a setup or hold violation.
|
This may be due to a setup or hold violation.
|
|
|
----------------------------------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------------------------------
|
Constraint | Check | Worst Case | Best Case | Timing | Timing
|
Constraint | Check | Worst Case | Best Case | Timing | Timing
|
| | Slack | Achievable | Errors | Score
|
| | Slack | Achievable | Errors | Score
|
----------------------------------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------------------------------
|
Autotimespec constraint for clock net gcl | SETUP | N/A| 5.299ns| N/A| 0
|
Autotimespec constraint for clock net gcl | SETUP | N/A| 4.888ns| N/A| 0
|
k_i_BUFGP | HOLD | 0.388ns| | 0| 0
|
k_i_BUFGP | HOLD | 0.378ns| | 0| 0
|
----------------------------------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------------------------------
|
Autotimespec constraint for clock net Ins | SETUP | N/A| 5.052ns| N/A| 0
|
Autotimespec constraint for clock net Ins | SETUP | N/A| 3.948ns| N/A| 0
|
t_spi_master_port/spi_clk_reg_BUFG | HOLD | 0.497ns| | 0| 0
|
t_spi_master_port/spi_clk_reg_BUFG | HOLD | 0.459ns| | 0| 0
|
----------------------------------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------------------------------
|
|
|
|
|
All constraints were met.
|
All constraints were met.
|
INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
|
INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
|
constraint is not analyzed due to the following: No paths covered by this
|
constraint is not analyzed due to the following: No paths covered by this
|
constraint; Other constraints intersect with this constraint; or This
|
constraint; Other constraints intersect with this constraint; or This
|
constraint was disabled by a Path Tracing Control. Please run the Timespec
|
constraint was disabled by a Path Tracing Control. Please run the Timespec
|
Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.
|
Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.
|
|
|
|
|
Generating Pad Report.
|
Generating Pad Report.
|
|
|
All signals are completely routed.
|
All signals are completely routed.
|
|
|
Total REAL time to PAR completion: 10 secs
|
Total REAL time to PAR completion: 10 secs
|
Total CPU time to PAR completion: 10 secs
|
Total CPU time to PAR completion: 10 secs
|
|
|
Peak Memory Usage: 269 MB
|
Peak Memory Usage: 264 MB
|
|
|
Placer: Placement generated during map.
|
Placer: Placement generated during map.
|
Routing: Completed - No errors found.
|
Routing: Completed - No errors found.
|
|
|
Number of error messages: 0
|
Number of error messages: 0
|
Number of warning messages: 1
|
Number of warning messages: 1
|
Number of info messages: 2
|
Number of info messages: 2
|
|
|
Writing design to file spi_master_atlys_top.ncd
|
Writing design to file spi_master_atlys_top.ncd
|
|
|
|
|
|
|
PAR done!
|
PAR done!
|
|
|
