OpenCores
URL https://opencores.org/ocsvn/spi_master_slave/spi_master_slave/trunk

Subversion Repositories spi_master_slave

[/] [spi_master_slave/] [trunk/] [syn/] [spi_master_atlys_top.syr] - Diff between revs 22 and 24

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Rev 22 Rev 24
Release 13.1 - xst O.40d (nt)
Release 13.1 - xst O.40d (nt)
Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp
--> Parameter TMPDIR set to xst/projnav.tmp
Total REAL time to Xst completion: 0.00 secs
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.08 secs
Total CPU time to Xst completion: 0.08 secs
--> Parameter xsthdpdir set to xst
--> Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 0.00 secs
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.08 secs
Total CPU time to Xst completion: 0.08 secs
--> Reading design: spi_master_atlys_top.prj
--> Reading design: spi_master_atlys_top.prj
TABLE OF CONTENTS
TABLE OF CONTENTS
  1) Synthesis Options Summary
  1) Synthesis Options Summary
  2) HDL Parsing
  2) HDL Parsing
  3) HDL Elaboration
  3) HDL Elaboration
  4) HDL Synthesis
  4) HDL Synthesis
       4.1) HDL Synthesis Report
       4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
  5) Advanced HDL Synthesis
       5.1) Advanced HDL Synthesis Report
       5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  6) Low Level Synthesis
  7) Partition Report
  7) Partition Report
  8) Design Summary
  8) Design Summary
       8.1) Primitive and Black Box Usage
       8.1) Primitive and Black Box Usage
       8.2) Device utilization summary
       8.2) Device utilization summary
       8.3) Partition Resource Summary
       8.3) Partition Resource Summary
       8.4) Timing Report
       8.4) Timing Report
            8.4.1) Clock Information
            8.4.1) Clock Information
            8.4.2) Asynchronous Control Signals Information
            8.4.2) Asynchronous Control Signals Information
            8.4.3) Timing Summary
            8.4.3) Timing Summary
            8.4.4) Timing Details
            8.4.4) Timing Details
            8.4.5) Cross Clock Domains Report
            8.4.5) Cross Clock Domains Report
=========================================================================
=========================================================================
*                      Synthesis Options Summary                        *
*                      Synthesis Options Summary                        *
=========================================================================
=========================================================================
---- Source Parameters
---- Source Parameters
Input File Name                    : "spi_master_atlys_top.prj"
Input File Name                    : "spi_master_atlys_top.prj"
Input Format                       : mixed
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Ignore Synthesis Constraint File   : NO
---- Target Parameters
---- Target Parameters
Output File Name                   : "spi_master_atlys_top"
Output File Name                   : "spi_master_atlys_top"
Output Format                      : NGC
Output Format                      : NGC
Target Device                      : xc6slx45-2-csg324
Target Device                      : xc6slx45-2-csg324
---- Source Options
---- Source Options
Top Module Name                    : spi_master_atlys_top
Top Module Name                    : spi_master_atlys_top
Automatic FSM Extraction           : YES
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Gray
FSM Encoding Algorithm             : Gray
Safe Implementation                : No
Safe Implementation                : No
FSM Style                          : LUT
FSM Style                          : LUT
RAM Extraction                     : No
RAM Extraction                     : No
ROM Extraction                     : No
ROM Extraction                     : No
Shift Register Extraction          : NO
Shift Register Extraction          : NO
Resource Sharing                   : YES
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Asynchronous To Synchronous        : NO
Shift Register Minimum Size        : 2
Shift Register Minimum Size        : 2
Use DSP Block                      : Auto
Use DSP Block                      : Auto
Automatic Register Balancing       : No
Automatic Register Balancing       : No
---- Target Options
---- Target Options
LUT Combining                      : Area
LUT Combining                      : Area
Reduce Control Sets                : Auto
Reduce Control Sets                : Auto
Add IO Buffers                     : YES
Add IO Buffers                     : YES
Global Maximum Fanout              : 100000
Global Maximum Fanout              : 100000
Add Generic Clock Buffer(BUFG)     : 16
Add Generic Clock Buffer(BUFG)     : 16
Register Duplication               : YES
Register Duplication               : YES
Optimize Instantiated Primitives   : NO
Optimize Instantiated Primitives   : NO
Use Clock Enable                   : Auto
Use Clock Enable                   : Auto
Use Synchronous Set                : Auto
Use Synchronous Set                : Auto
Use Synchronous Reset              : Auto
Use Synchronous Reset              : Auto
Pack IO Registers into IOBs        : Auto
Pack IO Registers into IOBs        : Auto
Equivalent register Removal        : YES
Equivalent register Removal        : YES
---- General Options
---- General Options
Optimization Goal                  : Speed
Optimization Goal                  : Speed
Optimization Effort                : 2
Optimization Effort                : 2
Power Reduction                    : NO
Power Reduction                    : NO
Keep Hierarchy                     : No
Keep Hierarchy                     : No
Netlist Hierarchy                  : As_Optimized
Netlist Hierarchy                  : As_Optimized
RTL Output                         : Yes
RTL Output                         : Yes
Global Optimization                : AllClockNets
Global Optimization                : AllClockNets
Read Cores                         : YES
Read Cores                         : YES
Write Timing Constraints           : NO
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Hierarchy Separator                : /
Bus Delimiter                      : <>
Bus Delimiter                      : <>
Case Specifier                     : Maintain
Case Specifier                     : Maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
BRAM Utilization Ratio             : 100
DSP48 Utilization Ratio            : 100
DSP48 Utilization Ratio            : 100
Auto BRAM Packing                  : NO
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5
Slice Utilization Ratio Delta      : 5
=========================================================================
=========================================================================
=========================================================================
=========================================================================
*                          HDL Parsing                                  *
*                          HDL Parsing                                  *
=========================================================================
=========================================================================
Parsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_slave.vhd" into library work
Parsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_slave.vhd" into library work
Parsing entity .
Parsing entity .
Parsing architecture  of entity .
Parsing architecture  of entity .
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_slave.vhd" Line 361: Case choice must be a locally static expression
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_slave.vhd" Line 361: Case choice must be a locally static expression
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_slave.vhd" Line 369: Case choice must be a locally static expression
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_slave.vhd" Line 369: Case choice must be a locally static expression
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_slave.vhd" Line 378: Case choice must be a locally static expression
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_slave.vhd" Line 378: Case choice must be a locally static expression
Parsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_master.vhd" into library work
Parsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master.vhd" into library work
Parsing entity .
Parsing entity .
Parsing architecture  of entity .
Parsing architecture  of entity .
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_master.vhd" Line 505: Case choice must be a locally static expression
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master.vhd" Line 505: Case choice must be a locally static expression
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_master.vhd" Line 513: Case choice must be a locally static expression
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master.vhd" Line 513: Case choice must be a locally static expression
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_master.vhd" Line 521: Case choice must be a locally static expression
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master.vhd" Line 521: Case choice must be a locally static expression
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_master.vhd" Line 530: Case choice must be a locally static expression
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master.vhd" Line 530: Case choice must be a locally static expression
Parsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\grp_debouncer.vhd" into library work
Parsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\grp_debouncer.vhd" into library work
Parsing entity .
Parsing entity .
Parsing architecture  of entity .
Parsing architecture  of entity .
Parsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_master_atlys_top.vhd" into library work
Parsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master_atlys_top.vhd" into library work
Parsing entity .
Parsing entity .
Parsing architecture  of entity .
Parsing architecture  of entity .
=========================================================================
=========================================================================
*                            HDL Elaboration                            *
*                            HDL Elaboration                            *
=========================================================================
=========================================================================
Elaborating entity  (architecture ) with generics from library .
Elaborating entity  (architecture ) with generics from library .
Elaborating entity  (architecture ) with generics from library .
Elaborating entity  (architecture ) with generics from library .
Elaborating entity  (architecture ) with generics from library .
Elaborating entity  (architecture ) with generics from library .
Elaborating entity  (architecture ) with generics from library .
Elaborating entity  (architecture ) with generics from library .
Elaborating entity  (architecture ) with generics from library .
Elaborating entity  (architecture ) with generics from library .
INFO:HDLCompiler:679 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_master_atlys_top.vhd" Line 459. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master_atlys_top.vhd" Line 460. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_master_atlys_top.vhd" Line 521. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master_atlys_top.vhd" Line 522. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_master_atlys_top.vhd" Line 571. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master_atlys_top.vhd" Line 572. Case statement is complete. others clause is never selected
 
 
=========================================================================
=========================================================================
*                           HDL Synthesis                               *
*                           HDL Synthesis                               *
=========================================================================
=========================================================================
Synthesizing Unit .
Synthesizing Unit .
    Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd".
    Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd".
        N = 8
        N = 8
        CPOL = '0'
        CPOL = '0'
        CPHA = '0'
        CPHA = '0'
        PREFETCH = 3
        PREFETCH = 3
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 184: Output port  of the instance  is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 185: Output port  of the instance  is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 184: Output port  of the instance  is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 185: Output port  of the instance  is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 184: Output port  of the instance  is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 185: Output port  of the instance  is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 184: Output port  of the instance  is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 185: Output port  of the instance  is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 184: Output port  of the instance  is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 185: Output port  of the instance  is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 184: Output port  of the instance  is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 185: Output port  of the instance  is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 184: Output port  of the instance  is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 185: Output port  of the instance  is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 184: Output port  of the instance  is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 185: Output port  of the instance  is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 184: Output port  of the instance  is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 185: Output port  of the instance  is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 184: Output port  of the instance  is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 185: Output port  of the instance  is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 205: Output port  of the instance  is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 206: Output port  of the instance  is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 205: Output port  of the instance  is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 206: Output port  of the instance  is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 205: Output port  of the instance  is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 206: Output port  of the instance  is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 205: Output port  of the instance  is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 206: Output port  of the instance  is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 224: Output port  of the instance  is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 225: Output port  of the instance  is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 233: Output port  of the instance  is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 234: Output port  of the instance  is unconnected or connected to loadless signal.
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 8-bit register for signal .
    Found 8-bit register for signal .
    Found 4-bit register for signal .
    Found 4-bit register for signal .
    Found 3-bit register for signal .
    Found 3-bit register for signal .
    Found 3-bit register for signal .
    Found 3-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 8-bit register for signal .
    Found 8-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 8-bit register for signal .
    Found 8-bit register for signal .
    Found 6-bit register for signal .
    Found 6-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 8-bit register for signal .
    Found 8-bit register for signal .
    Found 8-bit register for signal .
    Found 8-bit register for signal .
    Found 8-bit register for signal .
    Found 8-bit register for signal .
    Found 8-bit register for signal .
    Found 8-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found finite state machine  for signal .
    Found finite state machine  for signal .
    -----------------------------------------------------------------------
    -----------------------------------------------------------------------
    | States             | 7                                              |
    | States             | 7                                              |
    | Transitions        | 20                                             |
    | Transitions        | 20                                             |
    | Inputs             | 2                                              |
    | Inputs             | 2                                              |
    | Outputs            | 3                                              |
    | Outputs            | 3                                              |
    | Clock              | gclk_i (rising_edge)                           |
    | Clock              | pclk_i (rising_edge)                           |
    | Reset              | spi_ssel_o (positive)                          |
    | Reset              | spi_ssel_o (positive)                          |
    | Reset type         | synchronous                                    |
    | Reset type         | synchronous                                    |
    | Reset State        | st_reset                                       |
    | Reset State        | st_reset                                       |
    | Power Up State     | st_reset                                       |
    | Power Up State     | st_reset                                       |
    | Encoding           | Gray                                           |
    | Encoding           | Gray                                           |
    | Implementation     | LUT                                            |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    -----------------------------------------------------------------------
    Found finite state machine  for signal .
    Found finite state machine  for signal .
    -----------------------------------------------------------------------
    -----------------------------------------------------------------------
    | States             | 11                                             |
    | States             | 11                                             |
    | Transitions        | 36                                             |
    | Transitions        | 36                                             |
    | Inputs             | 11                                             |
    | Inputs             | 11                                             |
    | Outputs            | 10                                             |
    | Outputs            | 10                                             |
    | Clock              | gclk_i (rising_edge)                           |
    | Clock              | pclk_i (rising_edge)                           |
    | Reset              | clear (positive)                               |
    | Reset              | clear (positive)                               |
    | Reset type         | synchronous                                    |
    | Reset type         | synchronous                                    |
    | Reset State        | st_reset                                       |
    | Reset State        | st_reset                                       |
    | Power Up State     | st_reset                                       |
    | Power Up State     | st_reset                                       |
    | Encoding           | Gray                                           |
    | Encoding           | Gray                                           |
    | Implementation     | LUT                                            |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    -----------------------------------------------------------------------
INFO:Xst:1799 - State st_wait_spi_ack_2 is never reached in FSM .
INFO:Xst:1799 - State st_wait_spi_ack_2 is never reached in FSM .
    Found finite state machine  for signal .
    Found finite state machine  for signal .
    -----------------------------------------------------------------------
    -----------------------------------------------------------------------
    | States             | 8                                              |
    | States             | 8                                              |
    | Transitions        | 20                                             |
    | Transitions        | 20                                             |
    | Inputs             | 5                                              |
    | Inputs             | 5                                              |
    | Outputs            | 9                                              |
    | Outputs            | 9                                              |
    | Clock              | gclk_i (rising_edge)                           |
    | Clock              | pclk_i (rising_edge)                           |
    | Reset              | spi_ssel_o (positive)                          |
    | Reset              | spi_ssel_o (positive)                          |
    | Reset type         | synchronous                                    |
    | Reset type         | synchronous                                    |
    | Reset State        | st_reset                                       |
    | Reset State        | st_reset                                       |
    | Power Up State     | st_reset                                       |
    | Power Up State     | st_reset                                       |
    | Encoding           | Gray                                           |
    | Encoding           | Gray                                           |
    | Implementation     | LUT                                            |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    -----------------------------------------------------------------------
    Found 1-bit adder for signal > created at line 276.
    Found 1-bit adder for signal > created at line 277.
    Found 1-bit adder for signal > created at line 290.
    Found 1-bit adder for signal > created at line 291.
    Found 8-bit comparator equal for signal <_n0380> created at line 362
    Found 8-bit comparator equal for signal <_n0380> created at line 363
    Found 6-bit comparator equal for signal <_n0400> created at line 365
    Found 6-bit comparator equal for signal <_n0400> created at line 366
    Summary:
    Summary:
        inferred   2 Adder/Subtractor(s).
        inferred   2 Adder/Subtractor(s).
        inferred  71 D-type flip-flop(s).
        inferred  71 D-type flip-flop(s).
        inferred   2 Comparator(s).
        inferred   2 Comparator(s).
        inferred   5 Multiplexer(s).
        inferred   5 Multiplexer(s).
        inferred   3 Finite State Machine(s).
        inferred   3 Finite State Machine(s).
Unit  synthesized.
Unit  synthesized.
Synthesizing Unit .
Synthesizing Unit .
    Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master.vhd".
    Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master.vhd".
        N = 8
        N = 8
        CPOL = '0'
        CPOL = '0'
        CPHA = '0'
        CPHA = '0'
        PREFETCH = 3
        PREFETCH = 3
        SPI_2X_CLK_DIV = 1
        SPI_2X_CLK_DIV = 1
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 8-bit register for signal .
    Found 8-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 4-bit register for signal .
    Found 4-bit register for signal .
    Found 8-bit register for signal .
    Found 8-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 8-bit register for signal .
    Found 8-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit adder for signal > created at line 330.
    Found 1-bit adder for signal > created at line 330.
    Found 4-bit subtractor for signal > created at line 528.
    Found 4-bit subtractor for signal > created at line 528.
    Found 4-bit comparator greater for signal  created at line 521
    Found 4-bit comparator greater for signal  created at line 521
    Found 4-bit comparator greater for signal  created at line 521
    Found 4-bit comparator greater for signal  created at line 521
    Found 4-bit comparator greater for signal  created at line 530
    Found 4-bit comparator greater for signal  created at line 530
    Found 4-bit comparator greater for signal  created at line 530
    Found 4-bit comparator greater for signal  created at line 530
    Summary:
    Summary:
        inferred   2 Adder/Subtractor(s).
        inferred   2 Adder/Subtractor(s).
        inferred  52 D-type flip-flop(s).
        inferred  52 D-type flip-flop(s).
        inferred   4 Comparator(s).
        inferred   4 Comparator(s).
        inferred  13 Multiplexer(s).
        inferred  13 Multiplexer(s).
Unit  synthesized.
Unit  synthesized.
Synthesizing Unit .
Synthesizing Unit .
    Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_slave.vhd".
    Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_slave.vhd".
        N = 8
        N = 8
        CPOL = '0'
        CPOL = '0'
        CPHA = '0'
        CPHA = '0'
        PREFETCH = 3
        PREFETCH = 3
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 4-bit register for signal .
    Found 4-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 8-bit register for signal .
    Found 8-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 8-bit register for signal .
    Found 8-bit register for signal .
    Found 8-bit register for signal .
    Found 8-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 1-bit register for signal .
    Found 4-bit subtractor for signal > created at line 376.
    Found 4-bit subtractor for signal > created at line 376.
    Found 4-bit comparator greater for signal  created at line 369
    Found 4-bit comparator greater for signal  created at line 369
    Found 4-bit comparator greater for signal  created at line 369
    Found 4-bit comparator greater for signal  created at line 369
    Found 4-bit comparator greater for signal  created at line 378
    Found 4-bit comparator greater for signal  created at line 378
    Found 4-bit comparator greater for signal  created at line 378
    Found 4-bit comparator greater for signal  created at line 378
    Summary:
    Summary:
        inferred   1 Adder/Subtractor(s).
        inferred   1 Adder/Subtractor(s).
        inferred  44 D-type flip-flop(s).
        inferred  44 D-type flip-flop(s).
        inferred   4 Comparator(s).
        inferred   4 Comparator(s).
        inferred  22 Multiplexer(s).
        inferred  22 Multiplexer(s).
Unit  synthesized.
Unit  synthesized.
Synthesizing Unit .
Synthesizing Unit .
    Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/grp_debouncer.vhd".
    Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/grp_debouncer.vhd".
        N = 8
        N = 8
        CNT_VAL = 20000
        CNT_VAL = 200
    Found 8-bit register for signal .
    Found 8-bit register for signal .
    Found 8-bit register for signal .
    Found 8-bit register for signal .
 
    Found 1-bit register for signal .
    Found 8-bit register for signal .
    Found 8-bit register for signal .
    Found 15-bit register for signal .
    Found 8-bit register for signal .
    Found 16-bit adder for signal  created at line 162.
    Found 9-bit adder for signal  created at line 167.
    Found 8-bit comparator not equal for signal  created at line 184
    Found 8-bit comparator not equal for signal  created at line 192
    Found 8-bit comparator not equal for signal  created at line 190
    Found 8-bit comparator not equal for signal  created at line 194
    Summary:
    Summary:
        inferred   1 Adder/Subtractor(s).
        inferred   1 Adder/Subtractor(s).
        inferred  39 D-type flip-flop(s).
        inferred  33 D-type flip-flop(s).
        inferred   2 Comparator(s).
        inferred   2 Comparator(s).
Unit  synthesized.
Unit  synthesized.
Synthesizing Unit .
Synthesizing Unit .
    Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/grp_debouncer.vhd".
    Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/grp_debouncer.vhd".
        N = 6
        N = 6
        CNT_VAL = 20000
        CNT_VAL = 200
    Found 6-bit register for signal .
    Found 6-bit register for signal .
    Found 6-bit register for signal .
    Found 6-bit register for signal .
 
    Found 1-bit register for signal .
    Found 6-bit register for signal .
    Found 6-bit register for signal .
    Found 15-bit register for signal .
    Found 8-bit register for signal .
    Found 16-bit adder for signal  created at line 162.
    Found 9-bit adder for signal  created at line 167.
    Found 6-bit comparator not equal for signal  created at line 184
    Found 6-bit comparator not equal for signal  created at line 192
    Found 6-bit comparator not equal for signal  created at line 190
    Found 6-bit comparator not equal for signal  created at line 194
    Summary:
    Summary:
        inferred   1 Adder/Subtractor(s).
        inferred   1 Adder/Subtractor(s).
        inferred  33 D-type flip-flop(s).
        inferred  27 D-type flip-flop(s).
        inferred   2 Comparator(s).
        inferred   2 Comparator(s).
Unit  synthesized.
Unit  synthesized.
=========================================================================
=========================================================================
HDL Synthesis Report
HDL Synthesis Report
Macro Statistics
Macro Statistics
# Adders/Subtractors                                   : 7
# Adders/Subtractors                                   : 7
 1-bit adder                                           : 3
 1-bit adder                                           : 3
 16-bit adder                                          : 2
 
 4-bit subtractor                                      : 2
 4-bit subtractor                                      : 2
# Registers                                            : 73
 9-bit adder                                           : 2
 1-bit register                                        : 49
# Registers                                            : 75
 15-bit register                                       : 2
 1-bit register                                        : 51
 4-bit register                                        : 2
 4-bit register                                        : 2
 6-bit register                                        : 4
 6-bit register                                        : 4
 8-bit register                                        : 16
 8-bit register                                        : 18
# Comparators                                          : 14
# Comparators                                          : 14
 4-bit comparator greater                              : 8
 4-bit comparator greater                              : 8
 6-bit comparator equal                                : 1
 6-bit comparator equal                                : 1
 6-bit comparator not equal                            : 2
 6-bit comparator not equal                            : 2
 8-bit comparator equal                                : 1
 8-bit comparator equal                                : 1
 8-bit comparator not equal                            : 2
 8-bit comparator not equal                            : 2
# Multiplexers                                         : 40
# Multiplexers                                         : 40
 1-bit 2-to-1 multiplexer                              : 13
 1-bit 2-to-1 multiplexer                              : 13
 4-bit 2-to-1 multiplexer                              : 12
 4-bit 2-to-1 multiplexer                              : 12
 8-bit 2-to-1 multiplexer                              : 15
 8-bit 2-to-1 multiplexer                              : 15
# FSMs                                                 : 3
# FSMs                                                 : 3
=========================================================================
=========================================================================
=========================================================================
=========================================================================
*                       Advanced HDL Synthesis                          *
*                       Advanced HDL Synthesis                          *
=========================================================================
=========================================================================
WARNING:Xst:1710 - FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
Synthesizing (advanced) Unit .
Synthesizing (advanced) Unit .
The following registers are absorbed into counter : 1 register on signal .
The following registers are absorbed into counter : 1 register on signal .
Unit  synthesized (advanced).
Unit  synthesized (advanced).
Synthesizing (advanced) Unit .
Synthesizing (advanced) Unit .
The following registers are absorbed into counter : 1 register on signal .
The following registers are absorbed into counter : 1 register on signal .
Unit  synthesized (advanced).
Unit  synthesized (advanced).
Synthesizing (advanced) Unit .
Synthesizing (advanced) Unit .
The following registers are absorbed into counter : 1 register on signal .
The following registers are absorbed into counter : 1 register on signal .
Unit  synthesized (advanced).
Unit  synthesized (advanced).
Synthesizing (advanced) Unit .
Synthesizing (advanced) Unit .
The following registers are absorbed into counter : 1 register on signal .
The following registers are absorbed into counter : 1 register on signal .
The following registers are absorbed into counter : 1 register on signal .
The following registers are absorbed into counter : 1 register on signal .
Unit  synthesized (advanced).
Unit  synthesized (advanced).
=========================================================================
=========================================================================
Advanced HDL Synthesis Report
Advanced HDL Synthesis Report
Macro Statistics
Macro Statistics
# Adders/Subtractors                                   : 2
# Adders/Subtractors                                   : 2
 4-bit subtractor                                      : 2
 4-bit subtractor                                      : 2
# Counters                                             : 5
# Counters                                             : 5
 1-bit up counter                                      : 3
 1-bit up counter                                      : 3
 15-bit up counter                                     : 2
 8-bit up counter                                      : 2
# Registers                                            : 206
# Registers                                            : 208
 Flip-Flops                                            : 206
 Flip-Flops                                            : 208
# Comparators                                          : 14
# Comparators                                          : 14
 4-bit comparator greater                              : 8
 4-bit comparator greater                              : 8
 6-bit comparator equal                                : 1
 6-bit comparator equal                                : 1
 6-bit comparator not equal                            : 2
 6-bit comparator not equal                            : 2
 8-bit comparator equal                                : 1
 8-bit comparator equal                                : 1
 8-bit comparator not equal                            : 2
 8-bit comparator not equal                            : 2
# Multiplexers                                         : 47
# Multiplexers                                         : 47
 1-bit 2-to-1 multiplexer                              : 21
 1-bit 2-to-1 multiplexer                              : 21
 4-bit 2-to-1 multiplexer                              : 12
 4-bit 2-to-1 multiplexer                              : 12
 8-bit 2-to-1 multiplexer                              : 14
 8-bit 2-to-1 multiplexer                              : 14
# FSMs                                                 : 3
# FSMs                                                 : 3
=========================================================================
=========================================================================
=========================================================================
=========================================================================
*                         Low Level Synthesis                           *
*                         Low Level Synthesis                           *
=========================================================================
=========================================================================
WARNING:Xst:1293 - FF/Latch  has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch  has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
INFO:Xst:2261 - The FF/Latch  in Unit  is equivalent to the following 2 FFs/Latches, which will be removed :  
INFO:Xst:2261 - The FF/Latch  in Unit  is equivalent to the following 2 FFs/Latches, which will be removed :  
WARNING:Xst:1710 - FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
Optimizing FSM  on signal  with Gray encoding.
Optimizing FSM  on signal  with Gray encoding.
--------------------------------------
--------------------------------------
 State                    | Encoding
 State                    | Encoding
--------------------------------------
--------------------------------------
 st_reset                 | 000
 st_reset                 | 000
 st_wait_spi_do_valid_1   | 001
 st_wait_spi_do_valid_1   | 001
 st_wait_spi_n_do_valid_1 | 011
 st_wait_spi_n_do_valid_1 | 011
 st_wait_spi_do_valid_2   | 010
 st_wait_spi_do_valid_2   | 010
 st_wait_spi_n_do_valid_2 | 110
 st_wait_spi_n_do_valid_2 | 110
 st_wait_spi_do_valid_3   | 111
 st_wait_spi_do_valid_3   | 111
 st_wait_spi_n_do_valid_3 | 101
 st_wait_spi_n_do_valid_3 | 101
--------------------------------------
--------------------------------------
Optimizing FSM  on signal  with Gray encoding.
Optimizing FSM  on signal  with Gray encoding.
----------------------------------
----------------------------------
 State                | Encoding
 State                | Encoding
----------------------------------
----------------------------------
 st_reset             | 0000
 st_reset             | 0000
 st_wait_spi_idle     | 0001
 st_wait_spi_idle     | 0001
 st_wait_new_switch   | 0011
 st_wait_new_switch   | 0011
 st_send_spi_data_sw  | 0110
 st_send_spi_data_sw  | 0110
 st_wait_spi_ack_sw   | 0111
 st_wait_spi_ack_sw   | 0111
 st_send_spi_data_1   | 0010
 st_send_spi_data_1   | 0010
 st_wait_spi_ack_1    | 0100
 st_wait_spi_ack_1    | 0100
 st_wait_spi_di_req_2 | 0101
 st_wait_spi_di_req_2 | 0101
 st_wait_spi_ack_2    | 1100
 st_wait_spi_ack_2    | 1100
 st_wait_spi_di_req_3 | 1101
 st_wait_spi_di_req_3 | 1101
 st_wait_spi_ack_3    | 1111
 st_wait_spi_ack_3    | 1111
----------------------------------
----------------------------------
Optimizing FSM  on signal  with Gray encoding.
Optimizing FSM  on signal  with Gray encoding.
------------------------------------
------------------------------------
 State                  | Encoding
 State                  | Encoding
------------------------------------
------------------------------------
 st_reset               | 000
 st_reset               | 000
 st_wait_spi_start      | 001
 st_wait_spi_start      | 001
 st_wait_spi_di_req_2   | 011
 st_wait_spi_di_req_2   | 011
 st_wait_spi_ack_2      | unreached
 st_wait_spi_ack_2      | unreached
 st_wait_spi_do_valid_1 | 010
 st_wait_spi_do_valid_1 | 010
 st_wait_spi_di_req_3   | 110
 st_wait_spi_di_req_3   | 110
 st_wait_spi_ack_3      | 111
 st_wait_spi_ack_3      | 111
 st_wait_spi_end        | 101
 st_wait_spi_end        | 101
------------------------------------
------------------------------------
WARNING:Xst:1426 - The value init of the FF/Latch spi_di_reg_s_6 hinder the constant cleaning in the block spi_master_atlys_top.
WARNING:Xst:1426 - The value init of the FF/Latch spi_di_reg_s_6 hinder the constant cleaning in the block spi_master_atlys_top.
   You should achieve better results by setting this init to 1.
   You should achieve better results by setting this init to 1.
WARNING:Xst:1426 - The value init of the FF/Latch spi_di_reg_s_4 hinder the constant cleaning in the block spi_master_atlys_top.
WARNING:Xst:1426 - The value init of the FF/Latch spi_di_reg_s_4 hinder the constant cleaning in the block spi_master_atlys_top.
   You should achieve better results by setting this init to 1.
   You should achieve better results by setting this init to 1.
WARNING:Xst:1426 - The value init of the FF/Latch spi_di_reg_s_0 hinder the constant cleaning in the block spi_master_atlys_top.
WARNING:Xst:1426 - The value init of the FF/Latch spi_di_reg_s_0 hinder the constant cleaning in the block spi_master_atlys_top.
   You should achieve better results by setting this init to 1.
   You should achieve better results by setting this init to 1.
INFO:Xst:2261 - The FF/Latch  in Unit  is equivalent to the following 2 FFs/Latches, which will be removed :  
INFO:Xst:2261 - The FF/Latch  in Unit  is equivalent to the following 2 FFs/Latches, which will be removed :  
INFO:Xst:2261 - The FF/Latch  in Unit  is equivalent to the following FF/Latch, which will be removed : 
INFO:Xst:2261 - The FF/Latch  in Unit  is equivalent to the following FF/Latch, which will be removed : 
Optimizing unit  ...
Optimizing unit  ...
Optimizing unit  ...
Optimizing unit  ...
Optimizing unit  ...
Optimizing unit  ...
Optimizing unit  ...
Optimizing unit  ...
Optimizing unit  ...
Optimizing unit  ...
 
WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
 
WARNING:Xst:2677 - Node  of sequential type is unconnected in block .
WARNING:Xst:1293 - FF/Latch  has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch  has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process.
INFO:Xst:2261 - The FF/Latch  in Unit  is equivalent to the following 2 FFs/Latches, which will be removed :  
INFO:Xst:2261 - The FF/Latch  in Unit  is equivalent to the following 2 FFs/Latches, which will be removed :  
INFO:Xst:2261 - The FF/Latch  in Unit  is equivalent to the following FF/Latch, which will be removed : 
INFO:Xst:2261 - The FF/Latch  in Unit  is equivalent to the following FF/Latch, which will be removed : 
INFO:Xst:2261 - The FF/Latch  in Unit  is equivalent to the following FF/Latch, which will be removed : 
INFO:Xst:2261 - The FF/Latch  in Unit  is equivalent to the following FF/Latch, which will be removed : 
INFO:Xst:3203 - The FF/Latch  in Unit  is the opposite to the following 2 FFs/Latches, which will be removed :  
INFO:Xst:3203 - The FF/Latch  in Unit  is the opposite to the following 2 FFs/Latches, which will be removed :  
Mapping all equations...
Mapping all equations...
Building and optimizing final netlist ...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block spi_master_atlys_top, actual ratio is 1.
Found area constraint ratio of 100 (+ 5) on block spi_master_atlys_top, actual ratio is 1.
FlipFlop Inst_spi_slave_port/state_reg_0 has been replicated 1 time(s)
FlipFlop Inst_spi_slave_port/state_reg_0 has been replicated 1 time(s)
FlipFlop Inst_spi_slave_port/state_reg_1 has been replicated 1 time(s)
FlipFlop Inst_spi_slave_port/state_reg_1 has been replicated 1 time(s)
FlipFlop Inst_spi_slave_port/state_reg_2 has been replicated 2 time(s)
FlipFlop Inst_spi_slave_port/state_reg_2 has been replicated 2 time(s)
Final Macro Processing ...
Final Macro Processing ...
=========================================================================
=========================================================================
Final Register Report
Final Register Report
Macro Statistics
Macro Statistics
# Registers                                            : 232
# Registers                                            : 218
 Flip-Flops                                            : 232
 Flip-Flops                                            : 218
 
 
=========================================================================
=========================================================================
=========================================================================
=========================================================================
*                           Partition Report                            *
*                           Partition Report                            *
=========================================================================
=========================================================================
Partition Implementation Status
Partition Implementation Status
-------------------------------
-------------------------------
  No Partitions were found in this design.
  No Partitions were found in this design.
-------------------------------
-------------------------------
=========================================================================
=========================================================================
*                            Design Summary                             *
*                            Design Summary                             *
=========================================================================
=========================================================================
Top Level Output File Name         : spi_master_atlys_top.ngc
Top Level Output File Name         : spi_master_atlys_top.ngc
Primitive and Black Box Usage:
Primitive and Black Box Usage:
------------------------------
------------------------------
# BELS                             : 259
# BELS                             : 202
#      GND                         : 1
#      GND                         : 1
#      INV                         : 4
#      INV                         : 4
#      LUT1                        : 28
#      LUT1                        : 14
#      LUT2                        : 3
#      LUT2                        : 4
#      LUT3                        : 26
#      LUT3                        : 28
#      LUT4                        : 17
#      LUT4                        : 17
#      LUT5                        : 62
#      LUT5                        : 54
#      LUT6                        : 55
#      LUT6                        : 45
#      MUXCY                       : 28
#      MUXCY                       : 14
#      MUXF7                       : 4
#      MUXF7                       : 4
#      VCC                         : 1
#      VCC                         : 1
#      XORCY                       : 30
#      XORCY                       : 16
# FlipFlops/Latches                : 232
# FlipFlops/Latches                : 218
#      FD                          : 97
#      FD                          : 84
#      FD_1                        : 1
#      FD_1                        : 1
#      FDC                         : 8
#      FDC                         : 8
#      FDE                         : 111
#      FDE                         : 110
#      FDP_1                       : 1
#      FDP_1                       : 1
#      FDR                         : 10
#      FDR                         : 10
#      FDRE                        : 4
#      FDRE                        : 4
# Clock Buffers                    : 2
# Clock Buffers                    : 3
#      BUFG                        : 1
#      BUFG                        : 1
#      BUFGP                       : 1
#      BUFGP                       : 2
# IO Buffers                       : 62
# IO Buffers                       : 62
#      IBUF                        : 14
#      IBUF                        : 14
#      OBUF                        : 48
#      OBUF                        : 48
Device utilization summary:
Device utilization summary:
---------------------------
---------------------------
Selected Device : 6slx45csg324-2
Selected Device : 6slx45csg324-2
Slice Logic Utilization:
Slice Logic Utilization:
 Number of Slice Registers:             232  out of  54576     0%
 Number of Slice Registers:             218  out of  54576     0%
 Number of Slice LUTs:                  195  out of  27288     0%
 Number of Slice LUTs:                  166  out of  27288     0%
    Number used as Logic:               195  out of  27288     0%
    Number used as Logic:               166  out of  27288     0%
 
 
Slice Logic Distribution:
Slice Logic Distribution:
 Number of LUT Flip Flop pairs used:    301
 Number of LUT Flip Flop pairs used:    272
   Number with an unused Flip Flop:      69  out of    301    22%
   Number with an unused Flip Flop:      54  out of    272    19%
   Number with an unused LUT:           106  out of    301    35%
   Number with an unused LUT:           106  out of    272    38%
   Number of fully used LUT-FF pairs:   126  out of    301    41%
   Number of fully used LUT-FF pairs:   112  out of    272    41%
   Number of unique control sets:        23
   Number of unique control sets:        24
 
 
IO Utilization:
IO Utilization:
 Number of IOs:                          63
 Number of IOs:                          64
 Number of bonded IOBs:                  63  out of    218    28%
 Number of bonded IOBs:                  64  out of    218    29%
 
 
Specific Feature Utilization:
Specific Feature Utilization:
 Number of BUFG/BUFGCTRLs:                2  out of     16    12%
 Number of BUFG/BUFGCTRLs:                3  out of     16    18%
 
 
---------------------------
---------------------------
Partition Resource Summary:
Partition Resource Summary:
---------------------------
---------------------------
  No Partitions were found in this design.
  No Partitions were found in this design.
---------------------------
---------------------------
=========================================================================
=========================================================================
Timing Report
Timing Report
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.
      GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
Clock Information:
------------------
------------------
-----------------------------------+------------------------+-------+
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
-----------------------------------+------------------------+-------+
gclk_i                             | BUFGP                  | 203   |
pclk_i                             | BUFGP                  | 161   |
 
sclk_i                             | BUFGP                  | 28    |
Inst_spi_master_port/spi_clk_reg   | BUFG                   | 29    |
Inst_spi_master_port/spi_clk_reg   | BUFG                   | 29    |
-----------------------------------+------------------------+-------+
-----------------------------------+------------------------+-------+
Asynchronous Control Signals Information:
Asynchronous Control Signals Information:
----------------------------------------
----------------------------------------
No asynchronous control signals found in this design
No asynchronous control signals found in this design
Timing Summary:
Timing Summary:
---------------
---------------
Speed Grade: -2
Speed Grade: -2
 
 
   Minimum period: 5.267ns (Maximum Frequency: 189.861MHz)
   Minimum period: 5.283ns (Maximum Frequency: 189.286MHz)
   Minimum input arrival time before clock: 2.083ns
   Minimum input arrival time before clock: 2.083ns
   Maximum output required time after clock: 7.216ns
   Maximum output required time after clock: 7.216ns
   Maximum combinational path delay: No path found
   Maximum combinational path delay: No path found
Timing Details:
Timing Details:
---------------
---------------
All values displayed in nanoseconds (ns)
All values displayed in nanoseconds (ns)
=========================================================================
=========================================================================
Timing constraint: Default period analysis for Clock 'gclk_i'
Timing constraint: Default period analysis for Clock 'pclk_i'
  Clock period: 5.267ns (frequency: 189.861MHz)
  Clock period: 5.283ns (frequency: 189.286MHz)
  Total number of paths / destination ports: 2605 / 280
  Total number of paths / destination ports: 1509 / 201
-------------------------------------------------------------------------
-------------------------------------------------------------------------
Delay:               5.267ns (Levels of Logic = 4)
Delay:               5.283ns (Levels of Logic = 4)
  Source:            sw_reg_5 (FF)
  Source:            sw_reg_5 (FF)
  Destination:       m_wr_st_reg_FSM_FFd4 (FF)
  Destination:       btn_reg_0 (FF)
  Source Clock:      gclk_i rising
  Source Clock:      pclk_i rising
  Destination Clock: gclk_i rising
  Destination Clock: pclk_i rising
 
 
  Data Path: sw_reg_5 to m_wr_st_reg_FSM_FFd4
  Data Path: sw_reg_5 to btn_reg_0
                                Gate     Net
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    ----------------------------------------  ------------
     FDE:C->Q              3   0.525   1.196  sw_reg_5 (sw_reg_5)
     FDE:C->Q              3   0.525   1.196  sw_reg_5 (sw_reg_5)
     LUT6:I1->O            2   0.254   0.834  _n038082 (_n038081)
     LUT6:I1->O            2   0.254   0.834  _n038082 (_n038081)
     LUT6:I4->O            8   0.250   0.944  _n038083 (_n0380)
     LUT6:I4->O            3   0.250   0.766  _n038083 (_n0380)
     LUT5:I4->O            1   0.254   0.682  m_wr_st_reg_FSM_FFd2-In1 (m_wr_st_reg_FSM_FFd2-In1)
     LUT5:I4->O            6   0.254   0.876  _n0418_inv1_rstpot (_n0418_inv1_rstpot)
     LUT6:I5->O            1   0.254   0.000  m_wr_st_reg_FSM_FFd2-In2 (m_wr_st_reg_FSM_FFd2-In)
     LUT3:I2->O            1   0.254   0.000  btn_reg_0_dpot (btn_reg_0_dpot)
     FDR:D                     0.074          m_wr_st_reg_FSM_FFd2
     FDE:D                     0.074          btn_reg_0
 
    ----------------------------------------
 
    Total                      5.283ns (1.611ns logic, 3.672ns route)
 
                                       (30.5% logic, 69.5% route)
 
 
 
=========================================================================
 
Timing constraint: Default period analysis for Clock 'sclk_i'
 
  Clock period: 3.764ns (frequency: 265.675MHz)
 
  Total number of paths / destination ports: 173 / 52
 
-------------------------------------------------------------------------
 
Delay:               3.764ns (Levels of Logic = 1)
 
  Source:            Inst_spi_master_port/state_reg_3 (FF)
 
  Destination:       Inst_spi_master_port/sh_reg_7 (FF)
 
  Source Clock:      sclk_i rising
 
  Destination Clock: sclk_i rising
 
 
 
  Data Path: Inst_spi_master_port/state_reg_3 to Inst_spi_master_port/sh_reg_7
 
                                Gate     Net
 
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
 
    ----------------------------------------  ------------
 
     FDRE:C->Q            21   0.525   1.740  Inst_spi_master_port/state_reg_3 (Inst_spi_master_port/state_reg_3)
 
     LUT6:I1->O            8   0.254   0.943  Inst_spi_master_port/_n0278_inv1 (Inst_spi_master_port/_n0278_inv)
 
     FDE:CE                    0.302          Inst_spi_master_port/sh_reg_0
    ----------------------------------------
    ----------------------------------------
    Total                      5.267ns (1.611ns logic, 3.656ns route)
    Total                      3.764ns (1.081ns logic, 2.683ns route)
                                       (30.6% logic, 69.4% route)
                                       (28.7% logic, 71.3% route)
 
 
=========================================================================
=========================================================================
Timing constraint: Default period analysis for Clock 'Inst_spi_master_port/spi_clk_reg'
Timing constraint: Default period analysis for Clock 'Inst_spi_master_port/spi_clk_reg'
  Clock period: 4.344ns (frequency: 230.203MHz)
  Clock period: 4.344ns (frequency: 230.203MHz)
  Total number of paths / destination ports: 214 / 36
  Total number of paths / destination ports: 214 / 36
-------------------------------------------------------------------------
-------------------------------------------------------------------------
Delay:               2.172ns (Levels of Logic = 2)
Delay:               2.172ns (Levels of Logic = 2)
  Source:            Inst_spi_slave_port/state_reg_1_1 (FF)
  Source:            Inst_spi_slave_port/state_reg_1_1 (FF)
  Destination:       Inst_spi_slave_port/tx_bit_reg (FF)
  Destination:       Inst_spi_slave_port/tx_bit_reg (FF)
  Source Clock:      Inst_spi_master_port/spi_clk_reg rising
  Source Clock:      Inst_spi_master_port/spi_clk_reg rising
  Destination Clock: Inst_spi_master_port/spi_clk_reg falling
  Destination Clock: Inst_spi_master_port/spi_clk_reg falling
  Data Path: Inst_spi_slave_port/state_reg_1_1 to Inst_spi_slave_port/tx_bit_reg
  Data Path: Inst_spi_slave_port/state_reg_1_1 to Inst_spi_slave_port/tx_bit_reg
                                Gate     Net
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    ----------------------------------------  ------------
     FDC:C->Q              2   0.525   1.156  Inst_spi_slave_port/state_reg_1_1 (Inst_spi_slave_port/state_reg_1_1)
     FDC:C->Q              2   0.525   1.156  Inst_spi_slave_port/state_reg_1_1 (Inst_spi_slave_port/state_reg_1_1)
     LUT6:I1->O            1   0.254   0.000  Inst_spi_slave_port/tx_bit_next3_F (N10)
     LUT6:I1->O            1   0.254   0.000  Inst_spi_slave_port/tx_bit_next3_F (N14)
     MUXF7:I0->O           1   0.163   0.000  Inst_spi_slave_port/tx_bit_next3 (Inst_spi_slave_port/tx_bit_next)
     MUXF7:I0->O           1   0.163   0.000  Inst_spi_slave_port/tx_bit_next3 (Inst_spi_slave_port/tx_bit_next)
     FD_1:D                    0.074          Inst_spi_slave_port/tx_bit_reg
     FD_1:D                    0.074          Inst_spi_slave_port/tx_bit_reg
    ----------------------------------------
    ----------------------------------------
    Total                      2.172ns (1.016ns logic, 1.156ns route)
    Total                      2.172ns (1.016ns logic, 1.156ns route)
                                       (46.8% logic, 53.2% route)
                                       (46.8% logic, 53.2% route)
=========================================================================
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'gclk_i'
Timing constraint: Default OFFSET IN BEFORE for Clock 'pclk_i'
  Total number of paths / destination ports: 14 / 14
  Total number of paths / destination ports: 14 / 14
-------------------------------------------------------------------------
-------------------------------------------------------------------------
Offset:              2.083ns (Levels of Logic = 1)
Offset:              2.083ns (Levels of Logic = 1)
  Source:            sw_i<7> (PAD)
  Source:            sw_i<7> (PAD)
  Destination:       Inst_sw_debouncer/reg_A_7 (FF)
  Destination:       Inst_sw_debouncer/reg_A_7 (FF)
  Destination Clock: gclk_i rising
  Destination Clock: pclk_i rising
 
 
  Data Path: sw_i<7> to Inst_sw_debouncer/reg_A_7
  Data Path: sw_i<7> to Inst_sw_debouncer/reg_A_7
                                Gate     Net
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    ----------------------------------------  ------------
     IBUF:I->O             1   1.328   0.681  sw_i_7_IBUF (sw_i_7_IBUF)
     IBUF:I->O             1   1.328   0.681  sw_i_7_IBUF (sw_i_7_IBUF)
     FD:D                      0.074          Inst_sw_debouncer/reg_A_7
     FD:D                      0.074          Inst_sw_debouncer/reg_A_7
    ----------------------------------------
    ----------------------------------------
    Total                      2.083ns (1.402ns logic, 0.681ns route)
    Total                      2.083ns (1.402ns logic, 0.681ns route)
                                       (67.3% logic, 32.7% route)
                                       (67.3% logic, 32.7% route)
=========================================================================
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'gclk_i'
Timing constraint: Default OFFSET OUT AFTER for Clock 'pclk_i'
  Total number of paths / destination ports: 37 / 31
  Total number of paths / destination ports: 17 / 16
-------------------------------------------------------------------------
-------------------------------------------------------------------------
Offset:              7.216ns (Levels of Logic = 3)
Offset:              5.464ns (Levels of Logic = 2)
  Source:            Inst_spi_master_port/state_reg_2 (FF)
  Source:            Inst_spi_master_port/wren (FF)
  Destination:       spi_mosi_o (PAD)
  Destination:       spi_mosi_o (PAD)
  Source Clock:      gclk_i rising
  Source Clock:      pclk_i rising
 
 
  Data Path: Inst_spi_master_port/state_reg_2 to spi_mosi_o
  Data Path: Inst_spi_master_port/wren to spi_mosi_o
                                Gate     Net
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    ----------------------------------------  ------------
     FDRE:C->Q            20   0.525   1.394  Inst_spi_master_port/state_reg_2 (Inst_spi_master_port/state_reg_2)
     FD:C->Q               8   0.525   1.052  Inst_spi_master_port/wren (Inst_spi_master_port/wren)
     LUT2:I0->O            2   0.250   1.156  Inst_spi_master_port/spi_mosi_o_SW0 (N0)
     LUT6:I4->O            2   0.250   0.725  Inst_spi_master_port/spi_mosi_o (spi_mosi_o_OBUF)
     LUT6:I1->O            2   0.254   0.725  Inst_spi_master_port/spi_mosi_o (spi_mosi_o_OBUF)
 
     OBUF:I->O                 2.912          spi_mosi_o_OBUF (spi_mosi_o)
     OBUF:I->O                 2.912          spi_mosi_o_OBUF (spi_mosi_o)
    ----------------------------------------
    ----------------------------------------
    Total                      7.216ns (3.941ns logic, 3.275ns route)
    Total                      5.464ns (3.687ns logic, 1.777ns route)
                                       (54.6% logic, 45.4% route)
                                       (67.5% logic, 32.5% route)
 
 
=========================================================================
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Inst_spi_master_port/spi_clk_reg'
Timing constraint: Default OFFSET OUT AFTER for Clock 'Inst_spi_master_port/spi_clk_reg'
  Total number of paths / destination ports: 19 / 18
  Total number of paths / destination ports: 19 / 18
-------------------------------------------------------------------------
-------------------------------------------------------------------------
Offset:              5.307ns (Levels of Logic = 2)
Offset:              5.307ns (Levels of Logic = 2)
  Source:            Inst_spi_slave_port/preload_miso (FF)
  Source:            Inst_spi_slave_port/preload_miso (FF)
  Destination:       spi_miso_o (PAD)
  Destination:       spi_miso_o (PAD)
  Source Clock:      Inst_spi_master_port/spi_clk_reg falling
  Source Clock:      Inst_spi_master_port/spi_clk_reg falling
  Data Path: Inst_spi_slave_port/preload_miso to spi_miso_o
  Data Path: Inst_spi_slave_port/preload_miso to spi_miso_o
                                Gate     Net
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    ----------------------------------------  ------------
     FDP_1:C->Q            2   0.525   0.954  Inst_spi_slave_port/preload_miso (Inst_spi_slave_port/preload_miso)
     FDP_1:C->Q            2   0.525   0.954  Inst_spi_slave_port/preload_miso (Inst_spi_slave_port/preload_miso)
     LUT3:I0->O            1   0.235   0.681  Inst_spi_slave_port/Mmux_spi_miso_o11 (spi_miso_o_OBUF)
     LUT3:I0->O            1   0.235   0.681  Inst_spi_slave_port/Mmux_spi_miso_o11 (spi_miso_o_OBUF)
     OBUF:I->O                 2.912          spi_miso_o_OBUF (spi_miso_o)
     OBUF:I->O                 2.912          spi_miso_o_OBUF (spi_miso_o)
    ----------------------------------------
    ----------------------------------------
    Total                      5.307ns (3.672ns logic, 1.635ns route)
    Total                      5.307ns (3.672ns logic, 1.635ns route)
                                       (69.2% logic, 30.8% route)
                                       (69.2% logic, 30.8% route)
=========================================================================
=========================================================================
 
Timing constraint: Default OFFSET OUT AFTER for Clock 'sclk_i'
 
  Total number of paths / destination ports: 20 / 16
 
-------------------------------------------------------------------------
 
Offset:              7.216ns (Levels of Logic = 3)
 
  Source:            Inst_spi_master_port/state_reg_2 (FF)
 
  Destination:       spi_mosi_o (PAD)
 
  Source Clock:      sclk_i rising
 
 
 
  Data Path: Inst_spi_master_port/state_reg_2 to spi_mosi_o
 
                                Gate     Net
 
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
 
    ----------------------------------------  ------------
 
     FDRE:C->Q            20   0.525   1.394  Inst_spi_master_port/state_reg_2 (Inst_spi_master_port/state_reg_2)
 
     LUT2:I0->O            2   0.250   1.156  Inst_spi_master_port/spi_mosi_o_SW0 (N4)
 
     LUT6:I1->O            2   0.254   0.725  Inst_spi_master_port/spi_mosi_o (spi_mosi_o_OBUF)
 
     OBUF:I->O                 2.912          spi_mosi_o_OBUF (spi_mosi_o)
 
    ----------------------------------------
 
    Total                      7.216ns (3.941ns logic, 3.275ns route)
 
                                       (54.6% logic, 45.4% route)
 
 
 
=========================================================================
 
 
Cross Clock Domains Report:
Cross Clock Domains Report:
--------------------------
--------------------------
Clock to Setup on destination clock Inst_spi_master_port/spi_clk_reg
Clock to Setup on destination clock Inst_spi_master_port/spi_clk_reg
--------------------------------+---------+---------+---------+---------+
--------------------------------+---------+---------+---------+---------+
                                | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
                                | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock                    |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
Source Clock                    |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
--------------------------------+---------+---------+---------+---------+
--------------------------------+---------+---------+---------+---------+
Inst_spi_master_port/spi_clk_reg|    3.682|         |    2.224|         |
Inst_spi_master_port/spi_clk_reg|    3.682|         |    2.224|         |
gclk_i                          |    4.633|         |    3.198|         |
pclk_i                          |    3.012|         |    2.135|         |
 
sclk_i                          |    4.633|         |    3.198|         |
 
--------------------------------+---------+---------+---------+---------+
 
 
 
Clock to Setup on destination clock pclk_i
 
--------------------------------+---------+---------+---------+---------+
 
                                | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
 
Source Clock                    |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
 
--------------------------------+---------+---------+---------+---------+
 
Inst_spi_master_port/spi_clk_reg|    2.078|         |         |         |
 
pclk_i                          |    5.283|         |         |         |
 
sclk_i                          |    3.198|         |         |         |
--------------------------------+---------+---------+---------+---------+
--------------------------------+---------+---------+---------+---------+
 
 
Clock to Setup on destination clock gclk_i
Clock to Setup on destination clock sclk_i
--------------------------------+---------+---------+---------+---------+
--------------------------------+---------+---------+---------+---------+
                                | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
                                | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock                    |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
Source Clock                    |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
--------------------------------+---------+---------+---------+---------+
--------------------------------+---------+---------+---------+---------+
Inst_spi_master_port/spi_clk_reg|    2.078|    1.855|         |         |
Inst_spi_master_port/spi_clk_reg|         |    1.855|         |         |
gclk_i                          |    5.267|         |         |         |
pclk_i                          |    3.244|         |         |         |
 
sclk_i                          |    3.764|         |         |         |
--------------------------------+---------+---------+---------+---------+
--------------------------------+---------+---------+---------+---------+
=========================================================================
=========================================================================
Total REAL time to Xst completion: 6.00 secs
Total REAL time to Xst completion: 6.00 secs
Total CPU time to Xst completion: 6.29 secs
Total CPU time to Xst completion: 6.39 secs
 
 
-->
-->
 
 
Total memory usage is 188108 kilobytes
Total memory usage is 179340 kilobytes
 
 
Number of errors   :    0 (   0 filtered)
Number of errors   :    0 (   0 filtered)
Number of warnings :   26 (   0 filtered)
Number of warnings :   28 (   0 filtered)
Number of infos    :   24 (   0 filtered)
Number of infos    :   24 (   0 filtered)
 
 

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