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[/] [spi_master_slave/] [trunk/] [syn/] [spi_master_atlys_top.vhd] - Diff between revs 10 and 11

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Line 13... Line 13...
--
--
--          See the "spi_master_atlys.ucf" file for pin assignments.
--          See the "spi_master_atlys.ucf" file for pin assignments.
--          The test circuit uses the VHDCI connector on the Atlys to implement a 16-pin debug port to be used
--          The test circuit uses the VHDCI connector on the Atlys to implement a 16-pin debug port to be used
--          with a Tektronix MSO2014. The 16 debug pins are brought to 2 8x2 headers that form a umbilical
--          with a Tektronix MSO2014. The 16 debug pins are brought to 2 8x2 headers that form a umbilical
--          digital pod port.
--          digital pod port.
--          The board switches are used to set the SPI_MASTER transmit data, and the SPI_SLAVE receive data drives the switch LEDs.
 
--          The pushbuttons drive the slave transmit data, and the master received data drives the parallel debug port.
 
--
--
------------------------------ REVISION HISTORY -----------------------------------------------------------------------
------------------------------ REVISION HISTORY -----------------------------------------------------------------------
--
--
-- 2011/07/02   v0.01.0010  [JD]    implemented a wire-through from switches to LEDs, just to test the toolchain. It worked!
-- 2011/07/02   v0.01.0010  [JD]    implemented a wire-through from switches to LEDs, just to test the toolchain. It worked!
-- 2011/07/03   v0.01.0020  [JD]    added clock input, and a simple LED blinker for each LED. 
-- 2011/07/03   v0.01.0020  [JD]    added clock input, and a simple LED blinker for each LED. 
Line 27... Line 25...
--                                  this change made the design go up to 288MHz, after synthesis.
--                                  this change made the design go up to 288MHz, after synthesis.
-- 2011/07/07   v0.03.0050  [JD]    implemented a 16pin umbilical port for the MSO2014 in the Atlys VmodBB board, and moved all
-- 2011/07/07   v0.03.0050  [JD]    implemented a 16pin umbilical port for the MSO2014 in the Atlys VmodBB board, and moved all
--                                  external monitoring pins to the VHDCI ports.
--                                  external monitoring pins to the VHDCI ports.
-- 2011/07/10   v1.10.0075  [JD]    verified spi_master_slave at 50MHz, 25MHz, 16.666MHz, 12.5MHz, 10MHz, 8.333MHz, 7.1428MHz, 
-- 2011/07/10   v1.10.0075  [JD]    verified spi_master_slave at 50MHz, 25MHz, 16.666MHz, 12.5MHz, 10MHz, 8.333MHz, 7.1428MHz, 
--                                  6.25MHz, 1MHz and 500kHz 
--                                  6.25MHz, 1MHz and 500kHz 
 
-- 2011/07/18   v1.12.0105  [JD]    spi_master.vhd changed to fix CPHA='1' clock glitch.  
--
--
--
--
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_arith.all;
 
 
entity spi_master_atlys_top is
entity spi_master_atlys_top is
    Port (
    Port (
        gclk_i : in std_logic := 'X';               -- board clock input 100MHz
        gclk_i : in std_logic := 'X';               -- board clock input 100MHz
        clear_i : in std_logic := '0';              -- btn used as clear signal
 
        --- SPI interface ---
        --- SPI interface ---
        spi_ssel_o : out std_logic;                 -- spi port SSEL
        spi_ssel_o : out std_logic;                 -- spi port SSEL
        spi_sck_o : out std_logic;                  -- spi port SCK
        spi_sck_o : out std_logic;                  -- spi port SCK
        spi_mosi_o : out std_logic;                 -- spi port MOSI
        spi_mosi_o : out std_logic;                 -- spi port MOSI
        spi_miso_o : out std_logic;                 -- spi port MISO
        spi_miso_o : out std_logic;                 -- spi port MISO
Line 55... Line 53...
        dbg_o : out std_logic_vector (7 downto 0);  -- 10 generic debug pins
        dbg_o : out std_logic_vector (7 downto 0);  -- 10 generic debug pins
        --- spi debug pins ---
        --- spi debug pins ---
        spi_rx_bit_m_o : out std_logic;             -- master rx bit feedback
        spi_rx_bit_m_o : out std_logic;             -- master rx bit feedback
        spi_rx_bit_s_o : out std_logic;             -- slave rx bit feedback
        spi_rx_bit_s_o : out std_logic;             -- slave rx bit feedback
        spi_do_valid_o : out std_logic;             -- spi data valid
        spi_do_valid_o : out std_logic;             -- spi data valid
        spi_di_req_o : out std_logic;               -- spi data request
        spi_di_req_o : out std_logic                -- spi data request
        spi_wren_o : out std_logic;                 -- spi write enable
--        spi_wren_o : out std_logic;                 -- spi write enable
        spi_wren_ack_o : out std_logic              -- spi write enable ack
--        spi_wren_ack_o : out std_logic              -- spi write enable ack
    );
    );
end spi_master_atlys_top;
end spi_master_atlys_top;
 
 
architecture behavioral of spi_master_atlys_top is
architecture behavioral of spi_master_atlys_top is
 
 
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    constant FSM_CE_DIV         : integer := 1;     -- fsm operates at 100MHz
    constant FSM_CE_DIV         : integer := 1;     -- fsm operates at 100MHz
    constant SPI_2X_CLK_DIV     : integer := 1;     -- 50MHz SPI clock
    constant SPI_2X_CLK_DIV     : integer := 1;     -- 50MHz SPI clock
    constant SAMP_CE_DIV        : integer := 1;     -- board signals sampled at 100MHz
    constant SAMP_CE_DIV        : integer := 1;     -- board signals sampled at 100MHz
    -- spi port generics
    -- spi port generics
    constant N : integer := 8;                      -- 8 bits
    constant N : integer := 8;                      -- 8 bits
 
    constant CPOL   : std_logic := '0';
 
    constant CPHA   : std_logic := '0';
 
 
    -- button definitions
    -- button definitions
    constant btRESET    : integer := 0;             -- these are constants to use as btn_i(x)
    constant btRESET    : integer := 0;             -- these are constants to use as btn_i(x)
    constant btUP       : integer := 1;
    constant btUP       : integer := 1;
    constant btLEFT     : integer := 2;
    constant btLEFT     : integer := 2;
Line 159... Line 159...
    --=============================================================================================
    --=============================================================================================
    -- spi master port: 
    -- spi master port: 
    --      receives parallel data from the slide switches, transmits to slave port.
    --      receives parallel data from the slide switches, transmits to slave port.
    --      receives serial data from slave port, sends to 8bit parallel debug port.
    --      receives serial data from slave port, sends to 8bit parallel debug port.
    Inst_spi_master_port: entity work.spi_master(rtl)
    Inst_spi_master_port: entity work.spi_master(rtl)
        generic map (N => N, CPOL => '0', CPHA => '0', PREFETCH => 3, SPI_2X_CLK_DIV => SPI_2X_CLK_DIV)
        generic map (N => N, CPOL => CPOL, CPHA => CPHA, PREFETCH => 3, SPI_2X_CLK_DIV => SPI_2X_CLK_DIV)
        port map(
        port map(
            sclk_i => gclk_i,                   -- system clock is used for serial and parallel ports
            sclk_i => gclk_i,                   -- system clock is used for serial and parallel ports
            pclk_i => gclk_i,
            pclk_i => gclk_i,
            rst_i => spi_rst_reg,
            rst_i => spi_rst_reg,
            spi_ssel_o => spi_ssel,
            spi_ssel_o => spi_ssel,
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            di_i => spi_di_reg_m,
            di_i => spi_di_reg_m,
            do_valid_o => spi_do_valid_m,
            do_valid_o => spi_do_valid_m,
            do_o => spi_do_m,
            do_o => spi_do_m,
            rx_bit_reg_o => spi_rx_bit_m,
            rx_bit_reg_o => spi_rx_bit_m,
            wren_i => spi_wren_reg_m,
            wren_i => spi_wren_reg_m,
            wren_o => spi_wren_o,
--            wren_o => spi_wren_o,
            wren_ack_o => spi_wr_ack_m          -- monitor wren ack from inside spi port
            wren_ack_o => spi_wr_ack_m          -- monitor wren ack from inside spi port
        );
        );
 
 
    dbg(7 downto 0) <= spi_do_m(7 downto 0);    -- connect master received data to 8bit debug port
    dbg(7 downto 0) <= spi_do_m(7 downto 0);    -- connect master received data to 8bit debug port
    spi_rx_bit_m_o  <= spi_rx_bit_m;            -- connect rx_bit monitor for master port
    spi_rx_bit_m_o  <= spi_rx_bit_m;            -- connect rx_bit monitor for master port
 
 
    -- spi slave port
    -- spi slave port
    --      receives parallel data from the pushbuttons, transmits to master port.
    --      receives parallel data from the pushbuttons, transmits to master port.
    --      receives serial data from master port, sends to the 8 LEDs.
    --      receives serial data from master port, sends to the 8 LEDs.
    Inst_spi_slave_port: entity work.spi_slave(rtl)
    Inst_spi_slave_port: entity work.spi_slave(rtl)
        generic map (N => N, CPOL => '0', CPHA => '0', PREFETCH => 3)
        generic map (N => N, CPOL => CPOL, CPHA => CPHA, PREFETCH => 3)
        port map(
        port map(
            clk_i => gclk_i,
            clk_i => gclk_i,
            spi_ssel_i => spi_ssel,             -- generated by the spi master
            spi_ssel_i => spi_ssel,             -- generated by the spi master
            spi_sck_i => spi_sck,               -- generated by the spi master
            spi_sck_i => spi_sck,               -- generated by the spi master
            spi_mosi_i => spi_mosi,
            spi_mosi_i => spi_mosi,
Line 200... Line 200...
            rx_bit_reg_o => spi_rx_bit_s,
            rx_bit_reg_o => spi_rx_bit_s,
            do_valid_o => spi_do_valid_s,
            do_valid_o => spi_do_valid_s,
            do_o => spi_do_s
            do_o => spi_do_s
        );
        );
 
 
    spi_di_reg_s(7 downto 5) <= B"101";                 -- get the slave transmit data from pushbuttons
    spi_di_reg_s(7) <= btn_data(btLEFT);        -- get the slave transmit data from pushbuttons
    spi_di_reg_s(4 downto 0) <= btn_data(5 downto 1);
    spi_di_reg_s(6) <= btn_data(btCENTER);
 
    spi_di_reg_s(5 downto 1) <= B"10101";
 
    spi_di_reg_s(0) <= btn_data(btRIGHT);
    spi_wren_reg_s <= '1';                              -- fix wren to '1', for continuous load of transmit data
    spi_wren_reg_s <= '1';                              -- fix wren to '1', for continuous load of transmit data
    spi_rx_bit_s_o <= spi_rx_bit_s;                     -- connect rx_bit monitor for slave port
    spi_rx_bit_s_o <= spi_rx_bit_s;                     -- connect rx_bit monitor for slave port
 
 
    -- debounce for the input switches, with new data strobe output
    -- debounce for the input switches, with new data strobe output
    Inst_sw_debouncer: entity work.grp_debouncer(rtl)
    Inst_sw_debouncer: entity work.grp_debouncer(rtl)
Line 402... Line 404...
    spi_sck_o_proc:         spi_sck_o       <= spi_sck;
    spi_sck_o_proc:         spi_sck_o       <= spi_sck;
    spi_mosi_o_proc:        spi_mosi_o      <= spi_mosi;
    spi_mosi_o_proc:        spi_mosi_o      <= spi_mosi;
    spi_miso_o_proc:        spi_miso_o      <= spi_miso;
    spi_miso_o_proc:        spi_miso_o      <= spi_miso;
    spi_do_valid_o_proc:    spi_do_valid_o  <= spi_do_valid_m;
    spi_do_valid_o_proc:    spi_do_valid_o  <= spi_do_valid_m;
    spi_di_req_o_proc:      spi_di_req_o    <= spi_di_req_m;
    spi_di_req_o_proc:      spi_di_req_o    <= spi_di_req_m;
    spi_wren_ack_o_proc:    spi_wren_ack_o  <= spi_wr_ack_m;
--    spi_wren_ack_o_proc:    spi_wren_ack_o  <= spi_wr_ack_m;
    led_o_proc:             led_o           <= leds_reg;        -- connect leds_reg signal to LED outputs
    led_o_proc:             led_o           <= leds_reg;        -- connect leds_reg signal to LED outputs
 
 
    --=============================================================================================
    --=============================================================================================
    --  DEBUG LOGIC PROCESSES
    --  DEBUG LOGIC PROCESSES
    --=============================================================================================
    --=============================================================================================

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