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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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entity spi_master_atlys_top is
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entity spi_master_atlys_top is
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Generic (
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N : positive := 8; -- 8bit serial word length is default
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CPOL : std_logic := '0'; -- SPI mode selection (mode 0 default)
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CPHA : std_logic := '0'; -- CPOL = clock polarity, CPHA = clock phase.
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PREFETCH : positive := 3; -- prefetch lookahead cycles
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CLK_PERIOD : time := 10 ns; -- clock period for gclk_i (default 100MHz)
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DEBOUNCE_TIME : time := 200 us); -- switch debounce time (use 200 us for silicon, 2 us for simulation)
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Port (
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Port (
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gclk_i : in std_logic := 'X'; -- board clock input 100MHz
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gclk_i : in std_logic := 'X'; -- board clock input 100MHz
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--- SPI interface ---
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--- SPI interface ---
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spi_ssel_o : out std_logic; -- spi port SSEL
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spi_ssel_o : out std_logic; -- spi port SSEL
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spi_sck_o : out std_logic; -- spi port SCK
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spi_sck_o : out std_logic; -- spi port SCK
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Line 64... |
s_state_o : out std_logic_vector (3 downto 0); -- slave spi fsm state
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s_state_o : out std_logic_vector (3 downto 0); -- slave spi fsm state
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dbg_o : out std_logic_vector (11 downto 0) -- 12 generic debug pins
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dbg_o : out std_logic_vector (11 downto 0) -- 12 generic debug pins
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);
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);
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end spi_master_atlys_top;
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end spi_master_atlys_top;
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architecture behavioral of spi_master_atlys_top is
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architecture rtl of spi_master_atlys_top is
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--=============================================================================================
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--=============================================================================================
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-- Constants
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-- Constants
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--=============================================================================================
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--=============================================================================================
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-- clock divider count values from gclk_i (100MHz board clock)
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-- clock divider count values from gclk_i (100MHz board clock)
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-- these constants shall not be zero
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-- these constants shall not be zero
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constant FSM_CE_DIV : integer := 1; -- fsm operates at 100MHz
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constant FSM_CE_DIV : integer := 1; -- fsm operates at 100MHz
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constant SPI_2X_CLK_DIV : integer := 1; -- 50MHz SPI clock
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constant SPI_2X_CLK_DIV : integer := 1; -- 50MHz SPI clock
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constant SAMP_CE_DIV : integer := 1; -- board signals sampled at 100MHz
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constant SAMP_CE_DIV : integer := 1; -- board signals sampled at 100MHz
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-- spi port generics
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constant N : integer := 8; -- 8 bits
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constant CPOL : std_logic := '0';
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constant CPHA : std_logic := '0';
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-- button definitions
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-- button definitions
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constant btRESET : integer := 0; -- these are constants to use as btn_i(x)
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constant btRESET : integer := 0; -- these are constants to use as btn_i(x)
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constant btUP : integer := 1;
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constant btUP : integer := 1;
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constant btLEFT : integer := 2;
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constant btLEFT : integer := 2;
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--=============================================================================================
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--=============================================================================================
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-- COMPONENT INSTANTIATIONS FOR THE CORES UNDER TEST
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-- COMPONENT INSTANTIATIONS FOR THE CORES UNDER TEST
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--=============================================================================================
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--=============================================================================================
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-- spi master port: data and control signals driven by the master fsm
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-- spi master port: data and control signals driven by the master fsm
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Inst_spi_master_port: entity work.spi_master(rtl)
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Inst_spi_master_port: entity work.spi_master(rtl)
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generic map (N => N, CPOL => CPOL, CPHA => CPHA, PREFETCH => 3, SPI_2X_CLK_DIV => SPI_2X_CLK_DIV)
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generic map (N => N, CPOL => CPOL, CPHA => CPHA, PREFETCH => PREFETCH, SPI_2X_CLK_DIV => SPI_2X_CLK_DIV)
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port map(
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port map(
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sclk_i => gclk_i, -- system clock is used for serial and parallel ports
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sclk_i => gclk_i, -- system clock is used for serial and parallel ports
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pclk_i => gclk_i,
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pclk_i => gclk_i,
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rst_i => spi_rst_reg,
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rst_i => spi_rst_reg,
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spi_ssel_o => spi_ssel,
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spi_ssel_o => spi_ssel,
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state_dbg_o => spi_state_m -- debug: internal state register
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state_dbg_o => spi_state_m -- debug: internal state register
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);
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);
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-- spi slave port: data and control signals driven by the slave fsm
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-- spi slave port: data and control signals driven by the slave fsm
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Inst_spi_slave_port: entity work.spi_slave(rtl)
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Inst_spi_slave_port: entity work.spi_slave(rtl)
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generic map (N => N, CPOL => CPOL, CPHA => CPHA, PREFETCH => 3)
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generic map (N => N, CPOL => CPOL, CPHA => CPHA, PREFETCH => PREFETCH)
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port map(
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port map(
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clk_i => gclk_i,
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clk_i => gclk_i,
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spi_ssel_i => spi_ssel, -- driven by the spi master
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spi_ssel_i => spi_ssel, -- driven by the spi master
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spi_sck_i => spi_sck, -- driven by the spi master
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spi_sck_i => spi_sck, -- driven by the spi master
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spi_mosi_i => spi_mosi, -- driven by the spi master
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spi_mosi_i => spi_mosi, -- driven by the spi master
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Line 220... |
state_dbg_o => spi_state_s -- debug: internal state register
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state_dbg_o => spi_state_s -- debug: internal state register
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);
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);
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-- debounce for the input switches, with new data strobe output
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-- debounce for the input switches, with new data strobe output
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Inst_sw_debouncer: entity work.grp_debouncer(rtl)
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Inst_sw_debouncer: entity work.grp_debouncer(rtl)
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generic map (N => 8, CNT_VAL => 200) -- debounce 8 inputs with 200 us settling time
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generic map (N => 8, CNT_VAL => DEBOUNCE_TIME / CLK_PERIOD) -- debounce 8 inputs with selected settling time
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port map(
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port map(
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clk_i => gclk_i, -- system clock
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clk_i => gclk_i, -- system clock
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data_i => sw_i, -- noisy input data
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data_i => sw_i, -- noisy input data
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data_o => sw_data -- registered stable output data
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data_o => sw_data -- registered stable output data
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);
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);
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-- debounce for the input pushbuttons, with new data strobe output
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-- debounce for the input pushbuttons, with new data strobe output
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Inst_btn_debouncer: entity work.grp_debouncer(rtl)
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Inst_btn_debouncer: entity work.grp_debouncer(rtl)
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generic map (N => 6, CNT_VAL => 200) -- debounce 6 inputs with 200 us settling time
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generic map (N => 6, CNT_VAL => DEBOUNCE_TIME / CLK_PERIOD) -- debounce 6 inputs with selected settling time
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port map(
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port map(
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clk_i => gclk_i, -- system clock
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clk_i => gclk_i, -- system clock
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data_i => btn_i, -- noisy input data
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data_i => btn_i, -- noisy input data
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data_o => btn_data -- registered stable output data
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data_o => btn_data -- registered stable output data
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);
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);
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| Line 354... |
Line 357... |
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--=============================================================================================
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--=============================================================================================
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-- COMBINATORIAL NEXT-STATE LOGIC PROCESSES
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-- COMBINATORIAL NEXT-STATE LOGIC PROCESSES
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--=============================================================================================
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--=============================================================================================
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-- edge detector for new switch data
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-- edge detector for new switch data
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new_switch_proc: new_switch <= '1' when sw_data /= sw_reg else '0'; -- '1' for edge
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new_switch_proc: new_switch <= '1' when sw_data /= sw_reg else '0'; -- '1' for change edge
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-- edge detector for new button data
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-- edge detector for new button data
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new_button_proc: new_button <= '1' when btn_data /= btn_reg else '0'; -- '1' for edge
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new_button_proc: new_button <= '1' when btn_data /= btn_reg else '0'; -- '1' for change edge
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-- master port fsm state and combinatorial logic
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-- master port write fsmd logic
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fsm_m_wr_combi_proc: process ( m_wr_st_reg, spi_wren_reg_m, spi_di_reg_m, spi_di_req_m, spi_wr_ack_m,
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fsm_m_wr_combi_proc: process ( m_wr_st_reg, spi_wren_reg_m, spi_di_reg_m, spi_di_req_m, spi_wr_ack_m,
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spi_ssel_reg, spi_rst_reg, sw_data, sw_reg, new_switch, btn_data, btn_reg,
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spi_ssel_reg, spi_rst_reg, sw_data, sw_reg, new_switch, btn_data, btn_reg,
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new_button, clear) is
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new_button, clear) is
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begin
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begin
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spi_rst_next <= spi_rst_reg;
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spi_rst_next <= spi_rst_reg;
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Line 460... |
m_wr_st_next <= st_reset; -- state st_reset is safe state
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m_wr_st_next <= st_reset; -- state st_reset is safe state
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end case;
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end case;
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end process fsm_m_wr_combi_proc;
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end process fsm_m_wr_combi_proc;
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-- slave port fsm state and combinatorial logic
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-- slave port write fsmd logic
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fsm_s_wr_combi_proc: process ( s_wr_st_reg, spi_di_req_s, spi_wr_ack_s, spi_do_valid_s,
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fsm_s_wr_combi_proc: process ( s_wr_st_reg, spi_di_req_s, spi_wr_ack_s, spi_do_valid_s,
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spi_di_reg_s, spi_wren_reg_s, spi_ssel_reg) is
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spi_di_reg_s, spi_wren_reg_s, spi_ssel_reg) is
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begin
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begin
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spi_wren_next_s <= spi_wren_reg_s;
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spi_wren_next_s <= spi_wren_reg_s;
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spi_di_next_s <= spi_di_reg_s;
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spi_di_next_s <= spi_di_reg_s;
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s_wr_st_next <= s_wr_st_reg;
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s_wr_st_next <= s_wr_st_reg;
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case s_wr_st_reg is
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case s_wr_st_reg is
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when st_reset =>
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when st_reset =>
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spi_di_next_s <= X"D1"; -- write first data word
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spi_di_next_s <= X"51"; -- write first data word
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spi_wren_next_s <= '1'; -- set write enable
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spi_wren_next_s <= '1'; -- set write enable
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s_wr_st_next <= st_wait_spi_start;
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s_wr_st_next <= st_wait_spi_start;
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when st_wait_spi_start =>
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when st_wait_spi_start =>
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if spi_ssel_reg = '0' then -- wait for slave select
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if spi_ssel_reg = '0' then -- wait for slave select
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| Line 480... |
Line 483... |
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when st_wait_spi_di_req_2 =>
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when st_wait_spi_di_req_2 =>
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if spi_di_req_s = '1' then
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if spi_di_req_s = '1' then
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-- spi_di_next_s <= X"D2"; -- do not write on this cycle (cycle miss)
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-- spi_di_next_s <= X"D2"; -- do not write on this cycle (cycle miss)
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-- spi_wren_next_s <= '1';
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-- spi_wren_next_s <= '1';
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-- s_wr_st_next <= st_wait_spi_ack_2;
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s_wr_st_next <= st_wait_spi_do_valid_1;
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s_wr_st_next <= st_wait_spi_do_valid_1;
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end if;
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end if;
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when st_wait_spi_ack_2 => -- the actual write happens on this state
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when st_wait_spi_ack_2 => -- the actual write happens on this state
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if spi_wr_ack_s = '1' then
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if spi_wr_ack_s = '1' then
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Line 522... |
s_wr_st_next <= st_reset; -- state st_reset is safe state
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s_wr_st_next <= st_reset; -- state st_reset is safe state
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end case;
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end case;
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end process fsm_s_wr_combi_proc;
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end process fsm_s_wr_combi_proc;
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-- slave port fsm state and combinatorial logic
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-- slave port read fsmd logic
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fsm_s_rd_combi_proc: process ( s_rd_st_reg, spi_do_valid_s, spi_do_s, s_do_1_reg, s_do_2_reg, s_do_3_reg) is
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fsm_s_rd_combi_proc: process ( s_rd_st_reg, spi_do_valid_s, spi_do_s, s_do_1_reg, s_do_2_reg, s_do_3_reg) is
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begin
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begin
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s_do_1_next <= s_do_1_reg;
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s_do_1_next <= s_do_1_reg;
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s_do_2_next <= s_do_2_reg;
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s_do_2_next <= s_do_2_reg;
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s_do_3_next <= s_do_3_reg;
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s_do_3_next <= s_do_3_reg;
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| Line 605... |
Line 609... |
-- master signals mapped on dbg
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-- master signals mapped on dbg
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dbg(11) <= spi_wren_reg_m;
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dbg(11) <= spi_wren_reg_m;
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dbg(10) <= spi_wr_ack_m;
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dbg(10) <= spi_wr_ack_m;
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dbg(9) <= spi_di_req_m;
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dbg(9) <= spi_di_req_m;
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dbg(8) <= spi_do_valid_m;
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dbg(8) <= spi_do_valid_m;
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-- dbg(11 downto 8) <= spi_state_s;
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-- slave signals mapped on dbg
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-- slave signals mapped on dbg
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dbg(7) <= spi_wren_reg_s;
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dbg(7) <= spi_wren_reg_s;
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dbg(6) <= spi_wr_ack_s;
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dbg(6) <= spi_wr_ack_s;
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dbg(5) <= spi_di_req_s;
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dbg(5) <= spi_di_req_s;
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dbg(4) <= spi_do_valid_s;
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dbg(4) <= spi_do_valid_s;
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dbg(3 downto 0) <= spi_state_s;
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-- specific ports to test on testbench
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-- specific ports to test on testbench
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s_do_o <= spi_do_s;
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s_do_o <= spi_do_s;
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m_do_o <= spi_do_m;
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m_do_o <= spi_do_m;
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m_state_o <= spi_state_m; -- master spi fsm state
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m_state_o <= spi_state_m; -- master spi fsm state
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s_state_o <= spi_state_s; -- slave spi fsm state
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s_state_o <= spi_state_s; -- slave spi fsm state
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end behavioral;
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end rtl;
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No newline at end of file
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No newline at end of file
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