| Line 19... |
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------------------------------ REVISION HISTORY -----------------------------------------------------------------------
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------------------------------ REVISION HISTORY -----------------------------------------------------------------------
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--
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--
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-- 2011/07/02 v0.01.0010 [JD] implemented a wire-through from switches to LEDs, just to test the toolchain. It worked!
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-- 2011/07/02 v0.01.0010 [JD] implemented a wire-through from switches to LEDs, just to test the toolchain. It worked!
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-- 2011/07/03 v0.01.0020 [JD] added clock input, and a simple LED blinker for each LED.
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-- 2011/07/03 v0.01.0020 [JD] added clock input, and a simple LED blinker for each LED.
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-- 2011/07/03 v0.01.0030 [JD] added clear input, and instantiated a SPI_MASTER from my OpenCores project.
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-- 2011/07/03 v0.01.0030 [JD] added clear input, and instantiated a SPI_MASTER from my OpenCores project.
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-- 2011/07/04 v0.01.0040 [JD] changed all clocks to clock enables, and use the 100MHz board gclk_i to clock all registers.
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-- 2011/07/04 v0.01.0040 [JD] changed all clocks to clock enables, and use the 100MHz board pclk_i to clock all registers.
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-- this change made the design go up to 288MHz, after synthesis.
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-- this change made the design go up to 288MHz, after synthesis.
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-- 2011/07/07 v0.03.0050 [JD] implemented a 16pin umbilical port for the MSO2014 in the Atlys VmodBB board, and moved all
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-- 2011/07/07 v0.03.0050 [JD] implemented a 16pin umbilical port for the MSO2014 in the Atlys VmodBB board, and moved all
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-- external monitoring pins to the VHDCI ports.
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-- external monitoring pins to the VHDCI ports.
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-- 2011/07/10 v1.10.0075 [JD] verified spi_master_slave at 50MHz, 25MHz, 16.666MHz, 12.5MHz, 10MHz, 8.333MHz, 7.1428MHz,
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-- 2011/07/10 v1.10.0075 [JD] verified spi_master_slave at 50MHz, 25MHz, 16.666MHz, 12.5MHz, 10MHz, 8.333MHz, 7.1428MHz,
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-- 6.25MHz, 1MHz and 500kHz
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-- 6.25MHz, 1MHz and 500kHz
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| Line 40... |
Line 40... |
Generic (
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Generic (
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N : positive := 8; -- 8bit serial word length is default
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N : positive := 8; -- 8bit serial word length is default
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CPOL : std_logic := '0'; -- SPI mode selection (mode 0 default)
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CPOL : std_logic := '0'; -- SPI mode selection (mode 0 default)
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CPHA : std_logic := '0'; -- CPOL = clock polarity, CPHA = clock phase.
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CPHA : std_logic := '0'; -- CPOL = clock polarity, CPHA = clock phase.
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PREFETCH : positive := 3; -- prefetch lookahead cycles
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PREFETCH : positive := 3; -- prefetch lookahead cycles
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CLK_PERIOD : time := 10 ns; -- clock period for gclk_i (default 100MHz)
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CLK_PERIOD : time := 10 ns; -- clock period for pclk_i (default 100MHz)
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DEBOUNCE_TIME : time := 200 us); -- switch debounce time (use 200 us for silicon, 2 us for simulation)
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DEBOUNCE_TIME : time := 2 us); -- switch debounce time (use 200 us for silicon, 2 us for simulation)
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Port (
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Port (
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gclk_i : in std_logic := 'X'; -- board clock input 100MHz
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sclk_i : in std_logic := 'X'; -- board clock input 100MHz
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pclk_i : in std_logic := 'X'; -- board clock input 100MHz
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--- SPI interface ---
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--- SPI interface ---
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spi_ssel_o : out std_logic; -- spi port SSEL
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spi_ssel_o : out std_logic; -- spi port SSEL
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spi_sck_o : out std_logic; -- spi port SCK
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spi_sck_o : out std_logic; -- spi port SCK
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spi_mosi_o : out std_logic; -- spi port MOSI
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spi_mosi_o : out std_logic; -- spi port MOSI
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spi_miso_o : out std_logic; -- spi port MISO
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spi_miso_o : out std_logic; -- spi port MISO
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| Line 69... |
Line 70... |
architecture rtl of spi_master_atlys_top is
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architecture rtl of spi_master_atlys_top is
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|
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--=============================================================================================
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--=============================================================================================
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-- Constants
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-- Constants
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--=============================================================================================
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--=============================================================================================
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-- clock divider count values from gclk_i (100MHz board clock)
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-- clock divider count values from pclk_i (100MHz board clock)
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-- these constants shall not be zero
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-- these constants shall not be zero
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constant FSM_CE_DIV : integer := 1; -- fsm operates at 100MHz
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constant FSM_CE_DIV : integer := 1; -- fsm operates at 100MHz
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constant SPI_2X_CLK_DIV : integer := 1; -- 50MHz SPI clock
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constant SPI_2X_CLK_DIV : integer := 1; -- 50MHz SPI clock
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constant SAMP_CE_DIV : integer := 1; -- board signals sampled at 100MHz
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constant SAMP_CE_DIV : integer := 1; -- board signals sampled at 100MHz
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|
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| Line 182... |
Line 183... |
--=============================================================================================
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--=============================================================================================
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-- spi master port: data and control signals driven by the master fsm
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-- spi master port: data and control signals driven by the master fsm
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Inst_spi_master_port: entity work.spi_master(rtl)
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Inst_spi_master_port: entity work.spi_master(rtl)
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generic map (N => N, CPOL => CPOL, CPHA => CPHA, PREFETCH => PREFETCH, SPI_2X_CLK_DIV => SPI_2X_CLK_DIV)
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generic map (N => N, CPOL => CPOL, CPHA => CPHA, PREFETCH => PREFETCH, SPI_2X_CLK_DIV => SPI_2X_CLK_DIV)
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port map(
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port map(
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sclk_i => gclk_i, -- system clock is used for serial and parallel ports
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sclk_i => sclk_i, -- system clock is used for serial and parallel ports
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pclk_i => gclk_i,
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pclk_i => pclk_i,
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rst_i => spi_rst_reg,
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rst_i => spi_rst_reg,
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spi_ssel_o => spi_ssel,
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spi_ssel_o => spi_ssel,
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spi_sck_o => spi_sck,
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spi_sck_o => spi_sck,
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spi_mosi_o => spi_mosi,
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spi_mosi_o => spi_mosi,
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spi_miso_i => spi_miso, -- driven by the spi slave
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spi_miso_i => spi_miso, -- driven by the spi slave
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| Line 203... |
Line 204... |
|
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-- spi slave port: data and control signals driven by the slave fsm
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-- spi slave port: data and control signals driven by the slave fsm
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Inst_spi_slave_port: entity work.spi_slave(rtl)
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Inst_spi_slave_port: entity work.spi_slave(rtl)
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generic map (N => N, CPOL => CPOL, CPHA => CPHA, PREFETCH => PREFETCH)
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generic map (N => N, CPOL => CPOL, CPHA => CPHA, PREFETCH => PREFETCH)
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port map(
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port map(
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clk_i => gclk_i,
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clk_i => pclk_i,
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spi_ssel_i => spi_ssel, -- driven by the spi master
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spi_ssel_i => spi_ssel, -- driven by the spi master
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spi_sck_i => spi_sck, -- driven by the spi master
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spi_sck_i => spi_sck, -- driven by the spi master
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spi_mosi_i => spi_mosi, -- driven by the spi master
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spi_mosi_i => spi_mosi, -- driven by the spi master
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spi_miso_o => spi_miso,
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spi_miso_o => spi_miso,
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di_req_o => spi_di_req_s,
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di_req_o => spi_di_req_s,
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| Line 222... |
Line 223... |
|
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-- debounce for the input switches, with new data strobe output
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-- debounce for the input switches, with new data strobe output
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Inst_sw_debouncer: entity work.grp_debouncer(rtl)
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Inst_sw_debouncer: entity work.grp_debouncer(rtl)
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generic map (N => 8, CNT_VAL => DEBOUNCE_TIME / CLK_PERIOD) -- debounce 8 inputs with selected settling time
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generic map (N => 8, CNT_VAL => DEBOUNCE_TIME / CLK_PERIOD) -- debounce 8 inputs with selected settling time
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port map(
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port map(
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clk_i => gclk_i, -- system clock
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clk_i => pclk_i, -- system clock
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data_i => sw_i, -- noisy input data
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data_i => sw_i, -- noisy input data
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data_o => sw_data -- registered stable output data
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data_o => sw_data -- registered stable output data
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);
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);
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|
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-- debounce for the input pushbuttons, with new data strobe output
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-- debounce for the input pushbuttons, with new data strobe output
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Inst_btn_debouncer: entity work.grp_debouncer(rtl)
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Inst_btn_debouncer: entity work.grp_debouncer(rtl)
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generic map (N => 6, CNT_VAL => DEBOUNCE_TIME / CLK_PERIOD) -- debounce 6 inputs with selected settling time
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generic map (N => 6, CNT_VAL => DEBOUNCE_TIME / CLK_PERIOD) -- debounce 6 inputs with selected settling time
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port map(
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port map(
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clk_i => gclk_i, -- system clock
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clk_i => pclk_i, -- system clock
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data_i => btn_i, -- noisy input data
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data_i => btn_i, -- noisy input data
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data_o => btn_data -- registered stable output data
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data_o => btn_data -- registered stable output data
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);
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);
|
|
|
--=============================================================================================
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--=============================================================================================
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| Line 262... |
Line 263... |
-- clock.
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-- clock.
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-- input sample clock enable,
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-- input sample clock enable,
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-- fsm clock enable,
|
-- fsm clock enable,
|
-----------------------------------------------------------------------------------------------
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-----------------------------------------------------------------------------------------------
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-- generate the sampling clock enable from the 100MHz board input clock
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-- generate the sampling clock enable from the 100MHz board input clock
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samp_ce_gen_proc: process (gclk_i) is
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samp_ce_gen_proc: process (pclk_i) is
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variable clk_cnt : integer range SAMP_CE_DIV-1 downto 0 := 0;
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variable clk_cnt : integer range SAMP_CE_DIV-1 downto 0 := 0;
|
begin
|
begin
|
if gclk_i'event and gclk_i = '1' then
|
if pclk_i'event and pclk_i = '1' then
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if clk_cnt = SAMP_CE_DIV-1 then
|
if clk_cnt = SAMP_CE_DIV-1 then
|
samp_ce <= '1'; -- generate a single pulse every SAMP_CE_DIV clocks
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samp_ce <= '1'; -- generate a single pulse every SAMP_CE_DIV clocks
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clk_cnt := 0;
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clk_cnt := 0;
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else
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else
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samp_ce <= '0';
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samp_ce <= '0';
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clk_cnt := clk_cnt + 1;
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clk_cnt := clk_cnt + 1;
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end if;
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end if;
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end if;
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end if;
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end process samp_ce_gen_proc;
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end process samp_ce_gen_proc;
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-- generate the fsm clock enable from the 100MHz board input clock
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-- generate the fsm clock enable from the 100MHz board input clock
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fsm_ce_gen_proc: process (gclk_i) is
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fsm_ce_gen_proc: process (pclk_i) is
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variable clk_cnt : integer range FSM_CE_DIV-1 downto 0 := 0;
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variable clk_cnt : integer range FSM_CE_DIV-1 downto 0 := 0;
|
begin
|
begin
|
if gclk_i'event and gclk_i = '1' then
|
if pclk_i'event and pclk_i = '1' then
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if clk_cnt = FSM_CE_DIV-1 then
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if clk_cnt = FSM_CE_DIV-1 then
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fsm_ce <= '1'; -- generate a single pulse every FSM_CE_DIV clocks
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fsm_ce <= '1'; -- generate a single pulse every FSM_CE_DIV clocks
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clk_cnt := 0;
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clk_cnt := 0;
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else
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else
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fsm_ce <= '0';
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fsm_ce <= '0';
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| Line 294... |
Line 295... |
|
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--=============================================================================================
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--=============================================================================================
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-- INPUTS LOGIC
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-- INPUTS LOGIC
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--=============================================================================================
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--=============================================================================================
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-- registered inputs
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-- registered inputs
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samp_inputs_proc: process (gclk_i) is
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samp_inputs_proc: process (pclk_i) is
|
begin
|
begin
|
if gclk_i'event and gclk_i = '1' then
|
if pclk_i'event and pclk_i = '1' then
|
if samp_ce = '1' then
|
if samp_ce = '1' then
|
clear <= btn_data(btUP); -- clear is button UP
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clear <= btn_data(btUP); -- clear is button UP
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leds_reg <= leds_next; -- update LEDs with spi_slave received data
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leds_reg <= leds_next; -- update LEDs with spi_slave received data
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end if;
|
end if;
|
end if;
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end if;
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| Line 308... |
Line 309... |
|
|
--=============================================================================================
|
--=============================================================================================
|
-- REGISTER TRANSFER PROCESSES
|
-- REGISTER TRANSFER PROCESSES
|
--=============================================================================================
|
--=============================================================================================
|
-- fsm state and data registers: synchronous to the system clock
|
-- fsm state and data registers: synchronous to the system clock
|
fsm_reg_proc : process (gclk_i) is
|
fsm_reg_proc : process (pclk_i) is
|
begin
|
begin
|
-- FFD registers clocked on rising edge and cleared on sync 'clear'
|
-- FFD registers clocked on rising edge and cleared on sync 'clear'
|
if gclk_i'event and gclk_i = '1' then
|
if pclk_i'event and pclk_i = '1' then
|
if clear = '1' then -- sync reset
|
if clear = '1' then -- sync reset
|
m_wr_st_reg <= st_reset; -- only provide local reset for the state registers
|
m_wr_st_reg <= st_reset; -- only provide local reset for the state registers
|
else
|
else
|
if fsm_ce = '1' then
|
if fsm_ce = '1' then
|
m_wr_st_reg <= m_wr_st_next; -- master write state register update
|
m_wr_st_reg <= m_wr_st_next; -- master write state register update
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
-- FFD registers clocked on rising edge and cleared on ssel = '1'
|
-- FFD registers clocked on rising edge and cleared on ssel = '1'
|
if gclk_i'event and gclk_i = '1' then
|
if pclk_i'event and pclk_i = '1' then
|
if spi_ssel = '1' then -- sync reset
|
if spi_ssel = '1' then -- sync reset
|
s_wr_st_reg <= st_reset; -- only provide local reset for the state registers
|
s_wr_st_reg <= st_reset; -- only provide local reset for the state registers
|
s_rd_st_reg <= st_reset;
|
s_rd_st_reg <= st_reset;
|
else
|
else
|
if fsm_ce = '1' then
|
if fsm_ce = '1' then
|
| Line 333... |
Line 334... |
s_rd_st_reg <= s_rd_st_next; -- slave read state register update
|
s_rd_st_reg <= s_rd_st_next; -- slave read state register update
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
-- FFD registers clocked on rising edge, with no reset
|
-- FFD registers clocked on rising edge, with no reset
|
if gclk_i'event and gclk_i = '1' then
|
if pclk_i'event and pclk_i = '1' then
|
if fsm_ce = '1' then
|
if fsm_ce = '1' then
|
--------- master write fsm signals -----------
|
--------- master write fsm signals -----------
|
spi_wren_reg_m <= spi_wren_next_m;
|
spi_wren_reg_m <= spi_wren_next_m;
|
spi_di_reg_m <= spi_di_next_m;
|
spi_di_reg_m <= spi_di_next_m;
|
spi_rst_reg <= spi_rst_next;
|
spi_rst_reg <= spi_rst_next;
|
