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[/] [spi_master_slave/] [trunk/] [syn/] [spi_master_atlys_top_map.mrp] - Diff between revs 20 and 22

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Rev 20 Rev 22
Line 10... Line 10...
spi_master_atlys_top.pcf
spi_master_atlys_top.pcf
Target Device  : xc6slx45
Target Device  : xc6slx45
Target Package : csg324
Target Package : csg324
Target Speed   : -2
Target Speed   : -2
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date    : Wed Aug 10 22:56:29 2011
Mapped Date    : Mon Aug 29 00:08:18 2011
 
 
Design Summary
Design Summary
--------------
--------------
Number of errors:      0
Number of errors:      0
Number of warnings:    0
Number of warnings:    0
Slice Logic Utilization:
Slice Logic Utilization:
  Number of Slice Registers:                   209 out of  54,576    1%
  Number of Slice Registers:                   224 out of  54,576    1%
    Number used as Flip Flops:                 209
    Number used as Flip Flops:                 224
    Number used as Latches:                      0
    Number used as Latches:                      0
    Number used as Latch-thrus:                  0
    Number used as Latch-thrus:                  0
    Number used as AND/OR logics:                0
    Number used as AND/OR logics:                0
  Number of Slice LUTs:                        145 out of  27,288    1%
  Number of Slice LUTs:                        177 out of  27,288    1%
    Number used as logic:                      127 out of  27,288    1%
    Number used as logic:                      167 out of  27,288    1%
      Number using O6 output only:              75
      Number using O6 output only:             112
      Number using O5 output only:              13
      Number using O5 output only:              28
      Number using O5 and O6:                   39
      Number using O5 and O6:                   27
      Number used as ROM:                        0
      Number used as ROM:                        0
    Number used as Memory:                       4 out of   6,408    1%
    Number used as Memory:                       4 out of   6,408    1%
      Number used as Dual Port RAM:              0
      Number used as Dual Port RAM:              0
      Number used as Single Port RAM:            0
      Number used as Single Port RAM:            0
      Number used as Shift Register:             4
      Number used as Shift Register:             4
        Number using O6 output only:             4
        Number using O6 output only:             4
        Number using O5 output only:             0
        Number using O5 output only:             0
        Number using O5 and O6:                  0
        Number using O5 and O6:                  0
    Number used exclusively as route-thrus:     14
    Number used exclusively as route-thrus:      6
      Number with same-slice register load:     12
      Number with same-slice register load:      4
      Number with same-slice carry load:         2
      Number with same-slice carry load:         2
      Number with other load:                    0
      Number with other load:                    0
 
 
Slice Logic Distribution:
Slice Logic Distribution:
  Number of occupied Slices:                    91 out of   6,822    1%
  Number of occupied Slices:                   102 out of   6,822    1%
  Number of LUT Flip Flop pairs used:          225
  Number of LUT Flip Flop pairs used:          272
    Number with an unused Flip Flop:            49 out of     225   21%
    Number with an unused Flip Flop:            64 out of     272   23%
    Number with an unused LUT:                  80 out of     225   35%
    Number with an unused LUT:                  95 out of     272   34%
    Number of fully used LUT-FF pairs:          96 out of     225   42%
    Number of fully used LUT-FF pairs:         113 out of     272   41%
    Number of unique control sets:              25
    Number of unique control sets:              26
    Number of slice register sites lost
    Number of slice register sites lost
      to control set restrictions:              59 out of  54,576    1%
      to control set restrictions:              68 out of  54,576    1%
 
 
  A LUT Flip Flop pair for this architecture represents one LUT paired with
  A LUT Flip Flop pair for this architecture represents one LUT paired with
  one Flip Flop within a slice.  A control set is a unique combination of
  one Flip Flop within a slice.  A control set is a unique combination of
  clock, reset, set, and enable signals for a registered element.
  clock, reset, set, and enable signals for a registered element.
  The Slice Logic Distribution report is not meaningful if the design is
  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.
  over-mapped for a non-slice resource or if Placement fails.
 
 
IO Utilization:
IO Utilization:
  Number of bonded IOBs:                        63 out of     218   28%
  Number of bonded IOBs:                        63 out of     218   28%
    Number of LOCed IOBs:                       43 out of      63   68%
    Number of LOCed IOBs:                       47 out of      63   74%
 
 
Specific Feature Utilization:
Specific Feature Utilization:
  Number of RAMB16BWERs:                         0 out of     116    0%
  Number of RAMB16BWERs:                         0 out of     116    0%
  Number of RAMB8BWERs:                          0 out of     232    0%
  Number of RAMB8BWERs:                          0 out of     232    0%
  Number of BUFIO2/BUFIO2_2CLKs:                 0 out of      32    0%
  Number of BUFIO2/BUFIO2_2CLKs:                 0 out of      32    0%
Line 85... Line 85...
  Number of PLL_ADVs:                            0 out of       4    0%
  Number of PLL_ADVs:                            0 out of       4    0%
  Number of PMVs:                                0 out of       1    0%
  Number of PMVs:                                0 out of       1    0%
  Number of STARTUPs:                            0 out of       1    0%
  Number of STARTUPs:                            0 out of       1    0%
  Number of SUSPEND_SYNCs:                       0 out of       1    0%
  Number of SUSPEND_SYNCs:                       0 out of       1    0%
 
 
Average Fanout of Non-Clock Nets:                2.81
Average Fanout of Non-Clock Nets:                3.18
 
 
Peak Memory Usage:  303 MB
Peak Memory Usage:  298 MB
Total REAL time to MAP completion:  19 secs
Total REAL time to MAP completion:  17 secs
Total CPU time to MAP completion (all processors):   17 secs
Total CPU time to MAP completion (all processors):   17 secs
 
 
Table of Contents
Table of Contents
-----------------
-----------------
Section 1 - Errors
Section 1 - Errors
Line 140... Line 140...
   0.000 to 85.000 Celsius)
   0.000 to 85.000 Celsius)
INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to
INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to
   1.260 Volts)
   1.260 Volts)
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
   (.mrp).
   (.mrp).
INFO:Place:834 - Only a subset of IOs are locked. Out of 63 IOs, 43 are locked
INFO:Place:834 - Only a subset of IOs are locked. Out of 63 IOs, 47 are locked
   and 20 are not locked. If you would like to print the names of these IOs,
   and 16 are not locked. If you would like to print the names of these IOs,
   please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.
   please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.
INFO:Pack:1650 - Map created a placed design.
INFO:Pack:1650 - Map created a placed design.
 
 
Section 4 - Removed Logic Summary
Section 4 - Removed Logic Summary
---------------------------------
---------------------------------
   2 block(s) removed
   2 block(s) removed
   2 block(s) optimized away
   2 block(s) optimized away
   2 signal(s) removed
   2 signal(s) removed
  55 Block(s) redundant
  87 Block(s) redundant
 
 
Section 5 - Removed Logic
Section 5 - Removed Logic
-------------------------
-------------------------
 
 
The trimmed logic report below shows the logic removed from your design due to
The trimmed logic report below shows the logic removed from your design due to
Line 177... Line 177...
GND             XST_GND
GND             XST_GND
VCC             XST_VCC
VCC             XST_VCC
 
 
Redundant Block(s):
Redundant Block(s):
TYPE            BLOCK
TYPE            BLOCK
 
LUT1            Inst_sw_debouncer/Mcount_cnt_reg_cy<13>_rt
 
LUT1            Inst_sw_debouncer/Mcount_cnt_reg_cy<12>_rt
 
LUT1            Inst_sw_debouncer/Mcount_cnt_reg_cy<11>_rt
 
LUT1            Inst_sw_debouncer/Mcount_cnt_reg_cy<10>_rt
 
LUT1            Inst_sw_debouncer/Mcount_cnt_reg_cy<9>_rt
 
LUT1            Inst_sw_debouncer/Mcount_cnt_reg_cy<8>_rt
 
LUT1            Inst_sw_debouncer/Mcount_cnt_reg_cy<7>_rt
LUT1            Inst_sw_debouncer/Mcount_cnt_reg_cy<6>_rt
LUT1            Inst_sw_debouncer/Mcount_cnt_reg_cy<6>_rt
LUT1            Inst_sw_debouncer/Mcount_cnt_reg_cy<5>_rt
LUT1            Inst_sw_debouncer/Mcount_cnt_reg_cy<5>_rt
LUT1            Inst_sw_debouncer/Mcount_cnt_reg_cy<4>_rt
LUT1            Inst_sw_debouncer/Mcount_cnt_reg_cy<4>_rt
LUT1            Inst_sw_debouncer/Mcount_cnt_reg_cy<3>_rt
LUT1            Inst_sw_debouncer/Mcount_cnt_reg_cy<3>_rt
LUT1            Inst_sw_debouncer/Mcount_cnt_reg_cy<2>_rt
LUT1            Inst_sw_debouncer/Mcount_cnt_reg_cy<2>_rt
LUT1            Inst_sw_debouncer/Mcount_cnt_reg_cy<1>_rt
LUT1            Inst_sw_debouncer/Mcount_cnt_reg_cy<1>_rt
 
LUT1            Inst_btn_debouncer/Mcount_cnt_reg_cy<13>_rt
 
LUT1            Inst_btn_debouncer/Mcount_cnt_reg_cy<12>_rt
 
LUT1            Inst_btn_debouncer/Mcount_cnt_reg_cy<11>_rt
 
LUT1            Inst_btn_debouncer/Mcount_cnt_reg_cy<10>_rt
 
LUT1            Inst_btn_debouncer/Mcount_cnt_reg_cy<9>_rt
 
LUT1            Inst_btn_debouncer/Mcount_cnt_reg_cy<8>_rt
 
LUT1            Inst_btn_debouncer/Mcount_cnt_reg_cy<7>_rt
LUT1            Inst_btn_debouncer/Mcount_cnt_reg_cy<6>_rt
LUT1            Inst_btn_debouncer/Mcount_cnt_reg_cy<6>_rt
LUT1            Inst_btn_debouncer/Mcount_cnt_reg_cy<5>_rt
LUT1            Inst_btn_debouncer/Mcount_cnt_reg_cy<5>_rt
LUT1            Inst_btn_debouncer/Mcount_cnt_reg_cy<4>_rt
LUT1            Inst_btn_debouncer/Mcount_cnt_reg_cy<4>_rt
LUT1            Inst_btn_debouncer/Mcount_cnt_reg_cy<3>_rt
LUT1            Inst_btn_debouncer/Mcount_cnt_reg_cy<3>_rt
LUT1            Inst_btn_debouncer/Mcount_cnt_reg_cy<2>_rt
LUT1            Inst_btn_debouncer/Mcount_cnt_reg_cy<2>_rt
LUT1            Inst_btn_debouncer/Mcount_cnt_reg_cy<1>_rt
LUT1            Inst_btn_debouncer/Mcount_cnt_reg_cy<1>_rt
LUT1            Inst_sw_debouncer/Mcount_cnt_reg_xor<7>_rt
LUT1            Inst_sw_debouncer/Mcount_cnt_reg_xor<14>_rt
LUT1            Inst_btn_debouncer/Mcount_cnt_reg_xor<7>_rt
LUT1            Inst_btn_debouncer/Mcount_cnt_reg_xor<14>_rt
INV             ][1034_3_INV_0
INV             ][1211_3_INV_0
INV             ][269_110_INV_0
INV             ][1212_5_INV_0
INV             ][369_165_INV_0
INV             ][335_42_INV_0
INV             ][373_170_INV_0
INV             ][339_50_INV_0
INV             ][389_183_INV_0
INV             ][343_55_INV_0
INV             ][397_190_INV_0
INV             ][347_60_INV_0
INV             ][401_194_INV_0
INV             ][351_65_INV_0
INV             ][402_198_INV_0
INV             ][355_70_INV_0
INV             ][405_200_INV_0
INV             ][359_75_INV_0
INV             ][409_205_INV_0
INV             ][363_80_INV_0
INV             ][413_210_INV_0
INV             ][395_115_INV_0
INV             ][417_215_INV_0
INV             ][495_170_INV_0
INV             ][421_220_INV_0
INV             ][496_174_INV_0
INV             ][425_225_INV_0
INV             ][499_176_INV_0
INV             ][429_230_INV_0
INV             ][515_193_INV_0
INV             ][441_243_INV_0
INV             ][523_202_INV_0
INV             ][453_254_INV_0
INV             ][527_207_INV_0
INV             ][461_261_INV_0
INV             ][528_211_INV_0
INV             ][465_265_INV_0
INV             ][531_213_INV_0
INV             ][469_269_INV_0
INV             ][535_218_INV_0
INV             ][645_378_INV_0
INV             ][539_223_INV_0
INV             ][649_383_INV_0
INV             ][543_228_INV_0
INV             ][653_387_INV_0
INV             ][547_233_INV_0
INV             ][657_391_INV_0
INV             ][551_238_INV_0
INV             ][661_395_INV_0
INV             ][555_243_INV_0
INV             ][665_399_INV_0
INV             ][563_253_INV_0
INV             ][669_403_INV_0
INV             ][567_257_INV_0
INV             ][673_407_INV_0
INV             ][575_264_INV_0
INV             ][694_422_INV_0
INV             ][579_268_INV_0
INV             ][729_448_INV_0
INV             ][583_272_INV_0
INV             ][783_487_INV_0
INV             ][587_276_INV_0
INV             ][791_494_INV_0
INV             ][591_280_INV_0
INV             ][795_498_INV_0
INV             ][595_284_INV_0
INV             ][799_503_INV_0
INV             ][771_395_INV_0
INV             ][807_509_INV_0
INV             ][775_400_INV_0
INV             ][840_536_INV_0
INV             ][779_404_INV_0
INV             ][845_539_INV_0
INV             ][783_408_INV_0
INV             ][882_563_INV_0
INV             ][787_412_INV_0
INV             ][888_569_INV_0
INV             ][791_416_INV_0
INV             ][923_599_INV_0
INV             ][795_420_INV_0
INV             ][926_603_INV_0
INV             ][799_424_INV_0
 
INV             ][820_439_INV_0
 
INV             ][825_443_INV_0
 
INV             ][855_466_INV_0
 
INV             ][859_471_INV_0
 
INV             ][909_508_INV_0
 
INV             ][917_517_INV_0
 
INV             ][921_521_INV_0
 
INV             ][925_527_INV_0
 
INV             ][933_533_INV_0
 
INV             ][966_562_INV_0
 
INV             ][971_565_INV_0
 
INV             ][1008_588_INV_0
 
INV             ][1011_592_INV_0
 
INV             ][1014_596_INV_0
 
INV             ][1042_616_INV_0
 
INV             ][1051_628_INV_0
 
INV             ][1054_632_INV_0
 
INV             ][1057_636_INV_0
 
 
Section 6 - IOB Properties
Section 6 - IOB Properties
--------------------------
--------------------------
 
 
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
Line 350... Line 382...
------------------------------------
------------------------------------
+-----------------------------------------------------------------------------------------------------------------------------------+
+-----------------------------------------------------------------------------------------------------------------------------------+
| Clock Signal                           | Reset Signal           | Set Signal | Enable Signal  | Slice Load Count | Bel Load Count |
| Clock Signal                           | Reset Signal           | Set Signal | Enable Signal  | Slice Load Count | Bel Load Count |
+-----------------------------------------------------------------------------------------------------------------------------------+
+-----------------------------------------------------------------------------------------------------------------------------------+
| Inst_spi_master_port/spi_clk_reg_BUFG  |                        |            |                | 6                | 11             |
| Inst_spi_master_port/spi_clk_reg_BUFG  |                        |            |                | 6                | 11             |
| Inst_spi_master_port/spi_clk_reg_BUFG  |                        |            | lut1153_485    | 3                | 8              |
| Inst_spi_master_port/spi_clk_reg_BUFG  |                        |            | lut1117_506    | 3                | 8              |
| Inst_spi_master_port/spi_clk_reg_BUFG  | ][1032_0               |            |                | 2                | 3              |
| Inst_spi_master_port/spi_clk_reg_BUFG  | ][1209_0               |            |                | 2                | 2              |
| Inst_spi_master_port/spi_clk_reg_BUFG  | ][IN_virtPIBox_530_660 |            |                | 1                | 1              |
| Inst_spi_master_port/spi_clk_reg_BUFG  | ][IN_virtPIBox_574_736 |            |                | 1                | 2              |
+-----------------------------------------------------------------------------------------------------------------------------------+
+-----------------------------------------------------------------------------------------------------------------------------------+
| gclk_i_BUFGP                           |                        |            |                | 31               | 71             |
| gclk_i_BUFGP                           |                        |            |                | 36               | 85             |
| gclk_i_BUFGP                           |                        |            | GLOBAL_LOGIC1  | 1                | 4              |
| gclk_i_BUFGP                           |                        |            | GLOBAL_LOGIC1  | 1                | 4              |
| gclk_i_BUFGP                           |                        |            | ][210_37       | 1                | 8              |
| gclk_i_BUFGP                           |                        |            | ][336_48       | 2                | 8              |
| gclk_i_BUFGP                           |                        |            | ][242_80       | 2                | 6              |
| gclk_i_BUFGP                           |                        |            | ][496_174      | 2                | 8              |
| gclk_i_BUFGP                           |                        |            | ][402_198      | 2                | 8              |
| gclk_i_BUFGP                           |                        |            | ][528_211      | 2                | 8              |
| gclk_i_BUFGP                           |                        |            | ][691_420      | 2                | 4              |
| gclk_i_BUFGP                           |                        |            | ][817_437      | 3                | 4              |
| gclk_i_BUFGP                           |                        |            | lut403_108     | 1                | 2              |
| gclk_i_BUFGP                           |                        |            | lut263_47      | 2                | 6              |
| gclk_i_BUFGP                           |                        |            | lut415_115     | 2                | 8              |
| gclk_i_BUFGP                           |                        |            | lut350_113     | 1                | 2              |
| gclk_i_BUFGP                           |                        |            | lut456_132     | 2                | 8              |
| gclk_i_BUFGP                           |                        |            | lut362_120     | 2                | 8              |
| gclk_i_BUFGP                           |                        |            | lut497_149     | 2                | 8              |
| gclk_i_BUFGP                           |                        |            | lut403_137     | 2                | 8              |
| gclk_i_BUFGP                           |                        |            | lut539_168     | 2                | 8              |
| gclk_i_BUFGP                           |                        |            | lut444_154     | 2                | 8              |
| gclk_i_BUFGP                           |                        |            | lut703_275     | 1                | 8              |
| gclk_i_BUFGP                           |                        |            | lut649_291     | 2                | 8              |
| gclk_i_BUFGP                           |                        |            | lut825_325     | 2                | 6              |
| gclk_i_BUFGP                           |                        |            | lut772_342     | 2                | 6              |
| gclk_i_BUFGP                           |                        |            | lut916_362     | 2                | 8              |
| gclk_i_BUFGP                           |                        |            | lut863_379     | 2                | 8              |
| gclk_i_BUFGP                           |                        |            | lut958_381     | 2                | 8              |
| gclk_i_BUFGP                           |                        |            | lut905_398     | 3                | 8              |
| gclk_i_BUFGP                           |                        |            | spi_wren_reg_m | 1                | 8              |
| gclk_i_BUFGP                           |                        |            | spi_wren_reg_m | 2                | 8              |
| gclk_i_BUFGP                           |                        |            | spi_wren_reg_s | 1                | 2              |
| gclk_i_BUFGP                           |                        |            | spi_wren_reg_s | 1                | 2              |
| gclk_i_BUFGP                           | ][1032_0               |            |                | 4                | 6              |
| gclk_i_BUFGP                           | ][1209_0               |            |                | 2                | 6              |
| gclk_i_BUFGP                           | clear                  |            |                | 2                | 4              |
| gclk_i_BUFGP                           | clear                  |            |                | 2                | 4              |
| gclk_i_BUFGP                           | spi_rst_reg            |            | ][691_420      | 1                | 4              |
| gclk_i_BUFGP                           | spi_rst_reg            |            | ][817_437      | 1                | 4              |
+-----------------------------------------------------------------------------------------------------------------------------------+
+-----------------------------------------------------------------------------------------------------------------------------------+
| ~Inst_spi_master_port/spi_clk_reg_BUFG |                        |            |                | 1                | 1              |
| ~Inst_spi_master_port/spi_clk_reg_BUFG |                        |            |                | 1                | 1              |
 
| ~Inst_spi_master_port/spi_clk_reg_BUFG | ][1209_0               |            |                | 1                | 1              |
+-----------------------------------------------------------------------------------------------------------------------------------+
+-----------------------------------------------------------------------------------------------------------------------------------+
 
 
Section 13 - Utilization by Hierarchy
Section 13 - Utilization by Hierarchy
-------------------------------------
-------------------------------------
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| Module                | Partition | Slices*       | Slice Reg     | LUTs          | LUTRAM        | BRAM/FIFO | DSP48A1 | BUFG  | BUFIO | BUFR  | DCM   | PLL_ADV   | Full Hierarchical Name                     |
| Module                | Partition | Slices*       | Slice Reg     | LUTs          | LUTRAM        | BRAM/FIFO | DSP48A1 | BUFG  | BUFIO | BUFR  | DCM   | PLL_ADV   | Full Hierarchical Name                     |
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| spi_master_atlys_top/ |           | 64/121        | 71/209        | 109/119       | 0/4           | 0/0       | 0/0     | 1/2   | 0/0   | 0/0   | 0/0   | 0/0       | spi_master_atlys_top                       |
| spi_master_atlys_top/ |           | 68/139        | 71/224        | 135/145       | 0/4           | 0/0       | 0/0     | 1/2   | 0/0   | 0/0   | 0/0   | 0/0       | spi_master_atlys_top                       |
| +Inst_btn_debouncer   |           | 10/10         | 26/26         | 1/1           | 0/0           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | 0/0       | spi_master_atlys_top/Inst_btn_debouncer    |
| +Inst_btn_debouncer   |           | 14/14         | 33/33         | 1/1           | 0/0           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | 0/0       | spi_master_atlys_top/Inst_btn_debouncer    |
| +Inst_spi_master_port |           | 18/18         | 45/45         | 2/2           | 2/2           | 0/0       | 0/0     | 1/1   | 0/0   | 0/0   | 0/0   | 0/0       | spi_master_atlys_top/Inst_spi_master_port  |
| +Inst_spi_master_port |           | 21/21         | 45/45         | 2/2           | 2/2           | 0/0       | 0/0     | 1/1   | 0/0   | 0/0   | 0/0   | 0/0       | spi_master_atlys_top/Inst_spi_master_port  |
| +Inst_spi_slave_port  |           | 21/21         | 35/35         | 6/6           | 2/2           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | 0/0       | spi_master_atlys_top/Inst_spi_slave_port   |
| +Inst_spi_slave_port  |           | 23/23         | 36/36         | 6/6           | 2/2           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | 0/0       | spi_master_atlys_top/Inst_spi_slave_port   |
| +Inst_sw_debouncer    |           | 8/8           | 32/32         | 1/1           | 0/0           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | 0/0       | spi_master_atlys_top/Inst_sw_debouncer     |
| +Inst_sw_debouncer    |           | 13/13         | 39/39         | 1/1           | 0/0           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | 0/0       | spi_master_atlys_top/Inst_sw_debouncer     |
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
 
 
* Slices can be packed with basic elements from multiple hierarchies.
* Slices can be packed with basic elements from multiple hierarchies.
  Therefore, a slice will be counted in every hierarchical module
  Therefore, a slice will be counted in every hierarchical module
  that each of its packed basic elements belong to.
  that each of its packed basic elements belong to.

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