OpenCores
URL https://opencores.org/ocsvn/spi_master_slave/spi_master_slave/trunk

Subversion Repositories spi_master_slave

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<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>spi_master_atlys_top Project Status</B></TD></TR>
<TD ALIGN=CENTER COLSPAN='4'><B>spi_master_atlys_top Project Status (08/28/2011 - 23:35:14)</B></TD></TR>
<TR ALIGN=LEFT>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>spi_ms_atlys.xise</TD>
<TD>spi_ms_atlys.xise</TD>
<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
<TD> No Errors </TD>
<TD> No Errors </TD>
Line 17... Line 17...
</TR>
</TR>
<TR ALIGN=LEFT>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
<TD>xc6slx45-2csg324</TD>
<TD>xc6slx45-2csg324</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
<TD>&nbsp;</TD>
<TD>
 
No Errors</TD>
</TR>
</TR>
<TR ALIGN=LEFT>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 13.1</TD>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 13.1</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD>&nbsp;</TD>
<TD ALIGN=LEFT><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spimasterslave/spi_master_slave/trunk/syn\_xmsgs/*.xmsgs?&DataKey=Warning'>28 Warnings (0 new)</A></TD>
</TR>
</TR>
<TR ALIGN=LEFT>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
<TD>Balanced</TD>
<TD>Balanced</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
<TD>
<TD>
All Signals Completely Routed</TD>
&nbsp;</TD>
</TR>
</TR>
<TR ALIGN=LEFT>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
<TD>
<TD>&nbsp;</TD>
<A HREF_DISABLED='D:/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\spi_master_atlys_top.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD>
 
</TR>
</TR>
<TR ALIGN=LEFT>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
<TD>&nbsp;</TD>
<TD>
 
<A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spimasterslave/spi_master_slave/trunk/syn\spi_master_atlys_top_envsettings.html'>
 
System Settings</A>
 
</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
<TD>0 &nbsp;</TD>
<TD>&nbsp;&nbsp;</TD>
</TR>
</TR>
</TABLE>
</TABLE>
 
 
 
 
 
 
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='5'><B>Device Utilization Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary"><B>[-]</B></a></TD></TR>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Device Utilization Summary (estimated values)</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary(estimatedvalues)"><B>[-]</B></a></TD></TR>
<TR ALIGN=CENTER BGCOLOR='#FFFF99'>
<TR ALIGN=CENTER BGCOLOR='#FFFF99'>
<TD ALIGN=LEFT><B>Slice Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD>
<TD ALIGN=LEFT><B>Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD COLSPAN='2'><B>Utilization</B></TD></TR>
</TR>
 
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Registers</TD>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Registers</TD>
<TD ALIGN=RIGHT>209</TD>
<TD ALIGN=RIGHT>218</TD>
<TD ALIGN=RIGHT>54,576</TD>
<TD ALIGN=RIGHT>54576</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD ALIGN=RIGHT COLSPAN='2'>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
 
</TR>
 
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Flip Flops</TD>
 
<TD ALIGN=RIGHT>209</TD>
 
<TD>&nbsp;</TD>
 
<TD>&nbsp;</TD>
 
<TD COLSPAN='2'>&nbsp;</TD>
 
</TR>
 
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Latches</TD>
 
<TD ALIGN=RIGHT>0</TD>
 
<TD>&nbsp;</TD>
 
<TD>&nbsp;</TD>
 
<TD COLSPAN='2'>&nbsp;</TD>
 
</TR>
 
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Latch-thrus</TD>
 
<TD ALIGN=RIGHT>0</TD>
 
<TD>&nbsp;</TD>
 
<TD>&nbsp;</TD>
 
<TD COLSPAN='2'>&nbsp;</TD>
 
</TR>
 
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as AND/OR logics</TD>
 
<TD ALIGN=RIGHT>0</TD>
 
<TD>&nbsp;</TD>
 
<TD>&nbsp;</TD>
 
<TD COLSPAN='2'>&nbsp;</TD>
 
</TR>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD>
<TD ALIGN=RIGHT>145</TD>
<TD ALIGN=RIGHT>166</TD>
<TD ALIGN=RIGHT>27,288</TD>
<TD ALIGN=RIGHT>27288</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD ALIGN=RIGHT COLSPAN='2'>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of fully used LUT-FF pairs</TD>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as logic</TD>
<TD ALIGN=RIGHT>112</TD>
<TD ALIGN=RIGHT>127</TD>
<TD ALIGN=RIGHT>272</TD>
<TD ALIGN=RIGHT>27,288</TD>
<TD ALIGN=RIGHT COLSPAN='2'>41%</TD>
<TD ALIGN=RIGHT>1%</TD>
 
<TD COLSPAN='2'>&nbsp;</TD>
 
</TR>
 
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O6 output only</TD>
 
<TD ALIGN=RIGHT>75</TD>
 
<TD>&nbsp;</TD>
 
<TD>&nbsp;</TD>
 
<TD COLSPAN='2'>&nbsp;</TD>
 
</TR>
 
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 output only</TD>
 
<TD ALIGN=RIGHT>13</TD>
 
<TD>&nbsp;</TD>
 
<TD>&nbsp;</TD>
 
<TD COLSPAN='2'>&nbsp;</TD>
 
</TR>
 
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 and O6</TD>
 
<TD ALIGN=RIGHT>39</TD>
 
<TD>&nbsp;</TD>
 
<TD>&nbsp;</TD>
 
<TD COLSPAN='2'>&nbsp;</TD>
 
</TR>
 
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number used as ROM</TD>
 
<TD ALIGN=RIGHT>0</TD>
 
<TD>&nbsp;</TD>
 
<TD>&nbsp;</TD>
 
<TD COLSPAN='2'>&nbsp;</TD>
 
</TR>
 
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Memory</TD>
 
<TD ALIGN=RIGHT>4</TD>
 
<TD ALIGN=RIGHT>6,408</TD>
 
<TD ALIGN=RIGHT>1%</TD>
 
<TD COLSPAN='2'>&nbsp;</TD>
 
</TR>
 
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number used as Dual Port RAM</TD>
 
<TD ALIGN=RIGHT>0</TD>
 
<TD>&nbsp;</TD>
 
<TD>&nbsp;</TD>
 
<TD COLSPAN='2'>&nbsp;</TD>
 
</TR>
 
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number used as Single Port RAM</TD>
 
<TD ALIGN=RIGHT>0</TD>
 
<TD>&nbsp;</TD>
 
<TD>&nbsp;</TD>
 
<TD COLSPAN='2'>&nbsp;</TD>
 
</TR>
 
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number used as Shift Register</TD>
 
<TD ALIGN=RIGHT>4</TD>
 
<TD>&nbsp;</TD>
 
<TD>&nbsp;</TD>
 
<TD COLSPAN='2'>&nbsp;</TD>
 
</TR>
 
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O6 output only</TD>
 
<TD ALIGN=RIGHT>4</TD>
 
<TD>&nbsp;</TD>
 
<TD>&nbsp;</TD>
 
<TD COLSPAN='2'>&nbsp;</TD>
 
</TR>
 
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 output only</TD>
 
<TD ALIGN=RIGHT>0</TD>
 
<TD>&nbsp;</TD>
 
<TD>&nbsp;</TD>
 
<TD COLSPAN='2'>&nbsp;</TD>
 
</TR>
 
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 and O6</TD>
 
<TD ALIGN=RIGHT>0</TD>
 
<TD>&nbsp;</TD>
 
<TD>&nbsp;</TD>
 
<TD COLSPAN='2'>&nbsp;</TD>
 
</TR>
 
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used exclusively as route-thrus</TD>
 
<TD ALIGN=RIGHT>14</TD>
 
<TD>&nbsp;</TD>
 
<TD>&nbsp;</TD>
 
<TD COLSPAN='2'>&nbsp;</TD>
 
</TR>
 
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number with same-slice register load</TD>
 
<TD ALIGN=RIGHT>12</TD>
 
<TD>&nbsp;</TD>
 
<TD>&nbsp;</TD>
 
<TD COLSPAN='2'>&nbsp;</TD>
 
</TR>
 
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number with same-slice carry load</TD>
 
<TD ALIGN=RIGHT>2</TD>
 
<TD>&nbsp;</TD>
 
<TD>&nbsp;</TD>
 
<TD COLSPAN='2'>&nbsp;</TD>
 
</TR>
 
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number with other load</TD>
 
<TD ALIGN=RIGHT>0</TD>
 
<TD>&nbsp;</TD>
 
<TD>&nbsp;</TD>
 
<TD COLSPAN='2'>&nbsp;</TD>
 
</TR>
 
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD>
 
<TD ALIGN=RIGHT>91</TD>
 
<TD ALIGN=RIGHT>6,822</TD>
 
<TD ALIGN=RIGHT>1%</TD>
 
<TD COLSPAN='2'>&nbsp;</TD>
 
</TR>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of LUT Flip Flop pairs used</TD>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded IOBs</TD>
<TD ALIGN=RIGHT>225</TD>
 
<TD>&nbsp;</TD>
 
<TD>&nbsp;</TD>
 
<TD COLSPAN='2'>&nbsp;</TD>
 
</TR>
 
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number with an unused Flip Flop</TD>
 
<TD ALIGN=RIGHT>49</TD>
 
<TD ALIGN=RIGHT>225</TD>
 
<TD ALIGN=RIGHT>21%</TD>
 
<TD COLSPAN='2'>&nbsp;</TD>
 
</TR>
 
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number with an unused LUT</TD>
 
<TD ALIGN=RIGHT>80</TD>
 
<TD ALIGN=RIGHT>225</TD>
 
<TD ALIGN=RIGHT>35%</TD>
 
<TD COLSPAN='2'>&nbsp;</TD>
 
</TR>
 
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of fully used LUT-FF pairs</TD>
 
<TD ALIGN=RIGHT>96</TD>
 
<TD ALIGN=RIGHT>225</TD>
 
<TD ALIGN=RIGHT>42%</TD>
 
<TD COLSPAN='2'>&nbsp;</TD>
 
</TR>
 
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of unique control sets</TD>
 
<TD ALIGN=RIGHT>25</TD>
 
<TD>&nbsp;</TD>
 
<TD>&nbsp;</TD>
 
<TD COLSPAN='2'>&nbsp;</TD>
 
</TR>
 
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of slice register sites lost<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;to control set restrictions</TD>
 
<TD ALIGN=RIGHT>59</TD>
 
<TD ALIGN=RIGHT>54,576</TD>
 
<TD ALIGN=RIGHT>1%</TD>
 
<TD COLSPAN='2'>&nbsp;</TD>
 
</TR>
 
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded <A HREF_DISABLED='D:/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\spi_master_atlys_top_map.xrpt?&DataKey=IOBProperties'>IOBs</A></TD>
 
<TD ALIGN=RIGHT>63</TD>
<TD ALIGN=RIGHT>63</TD>
<TD ALIGN=RIGHT>218</TD>
<TD ALIGN=RIGHT>218</TD>
<TD ALIGN=RIGHT>28%</TD>
<TD ALIGN=RIGHT COLSPAN='2'>28%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
 
</TR>
 
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of LOCed IOBs</TD>
 
<TD ALIGN=RIGHT>43</TD>
 
<TD ALIGN=RIGHT>63</TD>
 
<TD ALIGN=RIGHT>68%</TD>
 
<TD COLSPAN='2'>&nbsp;</TD>
 
</TR>
 
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB16BWERs</TD>
 
<TD ALIGN=RIGHT>0</TD>
 
<TD ALIGN=RIGHT>116</TD>
 
<TD ALIGN=RIGHT>0%</TD>
 
<TD COLSPAN='2'>&nbsp;</TD>
 
</TR>
 
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB8BWERs</TD>
 
<TD ALIGN=RIGHT>0</TD>
 
<TD ALIGN=RIGHT>232</TD>
 
<TD ALIGN=RIGHT>0%</TD>
 
<TD COLSPAN='2'>&nbsp;</TD>
 
</TR>
 
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2/BUFIO2_2CLKs</TD>
 
<TD ALIGN=RIGHT>0</TD>
 
<TD ALIGN=RIGHT>32</TD>
 
<TD ALIGN=RIGHT>0%</TD>
 
<TD COLSPAN='2'>&nbsp;</TD>
 
</TR>
 
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2FB/BUFIO2FB_2CLKs</TD>
 
<TD ALIGN=RIGHT>0</TD>
 
<TD ALIGN=RIGHT>32</TD>
 
<TD ALIGN=RIGHT>0%</TD>
 
<TD COLSPAN='2'>&nbsp;</TD>
 
</TR>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFG/BUFGMUXs</TD>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFG/BUFGCTRLs</TD>
<TD ALIGN=RIGHT>2</TD>
<TD ALIGN=RIGHT>2</TD>
<TD ALIGN=RIGHT>16</TD>
<TD ALIGN=RIGHT>16</TD>
<TD ALIGN=RIGHT>12%</TD>
<TD ALIGN=RIGHT COLSPAN='2'>12%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
 
</TR>
 
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as BUFGs</TD>
 
<TD ALIGN=RIGHT>2</TD>
 
<TD>&nbsp;</TD>
 
<TD>&nbsp;</TD>
 
<TD COLSPAN='2'>&nbsp;</TD>
 
</TR>
 
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as BUFGMUX</TD>
 
<TD ALIGN=RIGHT>0</TD>
 
<TD>&nbsp;</TD>
 
<TD>&nbsp;</TD>
 
<TD COLSPAN='2'>&nbsp;</TD>
 
</TR>
 
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DCM/DCM_CLKGENs</TD>
 
<TD ALIGN=RIGHT>0</TD>
 
<TD ALIGN=RIGHT>8</TD>
 
<TD ALIGN=RIGHT>0%</TD>
 
<TD COLSPAN='2'>&nbsp;</TD>
 
</TR>
 
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ILOGIC2/ISERDES2s</TD>
 
<TD ALIGN=RIGHT>0</TD>
 
<TD ALIGN=RIGHT>376</TD>
 
<TD ALIGN=RIGHT>0%</TD>
 
<TD COLSPAN='2'>&nbsp;</TD>
 
</TR>
 
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of IODELAY2/IODRP2/IODRP2_MCBs</TD>
 
<TD ALIGN=RIGHT>0</TD>
 
<TD ALIGN=RIGHT>376</TD>
 
<TD ALIGN=RIGHT>0%</TD>
 
<TD COLSPAN='2'>&nbsp;</TD>
 
</TR>
 
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of OLOGIC2/OSERDES2s</TD>
 
<TD ALIGN=RIGHT>0</TD>
 
<TD ALIGN=RIGHT>376</TD>
 
<TD ALIGN=RIGHT>0%</TD>
 
<TD COLSPAN='2'>&nbsp;</TD>
 
</TR>
 
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BSCANs</TD>
 
<TD ALIGN=RIGHT>0</TD>
 
<TD ALIGN=RIGHT>4</TD>
 
<TD ALIGN=RIGHT>0%</TD>
 
<TD COLSPAN='2'>&nbsp;</TD>
 
</TR>
 
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFHs</TD>
 
<TD ALIGN=RIGHT>0</TD>
 
<TD ALIGN=RIGHT>256</TD>
 
<TD ALIGN=RIGHT>0%</TD>
 
<TD COLSPAN='2'>&nbsp;</TD>
 
</TR>
 
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFPLLs</TD>
 
<TD ALIGN=RIGHT>0</TD>
 
<TD ALIGN=RIGHT>8</TD>
 
<TD ALIGN=RIGHT>0%</TD>
 
<TD COLSPAN='2'>&nbsp;</TD>
 
</TR>
 
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFPLL_MCBs</TD>
 
<TD ALIGN=RIGHT>0</TD>
 
<TD ALIGN=RIGHT>4</TD>
 
<TD ALIGN=RIGHT>0%</TD>
 
<TD COLSPAN='2'>&nbsp;</TD>
 
</TR>
 
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DSP48A1s</TD>
 
<TD ALIGN=RIGHT>0</TD>
 
<TD ALIGN=RIGHT>58</TD>
 
<TD ALIGN=RIGHT>0%</TD>
 
<TD COLSPAN='2'>&nbsp;</TD>
 
</TR>
 
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ICAPs</TD>
 
<TD ALIGN=RIGHT>0</TD>
 
<TD ALIGN=RIGHT>1</TD>
 
<TD ALIGN=RIGHT>0%</TD>
 
<TD COLSPAN='2'>&nbsp;</TD>
 
</TR>
 
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of MCBs</TD>
 
<TD ALIGN=RIGHT>0</TD>
 
<TD ALIGN=RIGHT>2</TD>
 
<TD ALIGN=RIGHT>0%</TD>
 
<TD COLSPAN='2'>&nbsp;</TD>
 
</TR>
 
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PCILOGICSEs</TD>
 
<TD ALIGN=RIGHT>0</TD>
 
<TD ALIGN=RIGHT>2</TD>
 
<TD ALIGN=RIGHT>0%</TD>
 
<TD COLSPAN='2'>&nbsp;</TD>
 
</TR>
 
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PLL_ADVs</TD>
 
<TD ALIGN=RIGHT>0</TD>
 
<TD ALIGN=RIGHT>4</TD>
 
<TD ALIGN=RIGHT>0%</TD>
 
<TD COLSPAN='2'>&nbsp;</TD>
 
</TR>
 
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PMVs</TD>
 
<TD ALIGN=RIGHT>0</TD>
 
<TD ALIGN=RIGHT>1</TD>
 
<TD ALIGN=RIGHT>0%</TD>
 
<TD COLSPAN='2'>&nbsp;</TD>
 
</TR>
 
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of STARTUPs</TD>
 
<TD ALIGN=RIGHT>0</TD>
 
<TD ALIGN=RIGHT>1</TD>
 
<TD ALIGN=RIGHT>0%</TD>
 
<TD COLSPAN='2'>&nbsp;</TD>
 
</TR>
 
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of SUSPEND_SYNCs</TD>
 
<TD ALIGN=RIGHT>0</TD>
 
<TD ALIGN=RIGHT>1</TD>
 
<TD ALIGN=RIGHT>0%</TD>
 
<TD COLSPAN='2'>&nbsp;</TD>
 
</TR>
 
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Average Fanout of Non-Clock Nets</TD>
 
<TD ALIGN=RIGHT>2.81</TD>
 
<TD>&nbsp;</TD>
 
<TD>&nbsp;</TD>
 
<TD COLSPAN='2'>&nbsp;</TD>
 
</TR>
</TR>
</TABLE>
</TABLE>
 
 
 
 
 
 
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
 
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Performance Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=PerformanceSummary"><B>[-]</B></a></TD></TR>
 
<TR ALIGN=LEFT>
 
<TD BGCOLOR='#FFFF99'><B>Final Timing Score:</B></TD>
 
<TD>0 (Setup: 0, Hold: 0)</TD>
 
<TD BGCOLOR='#FFFF99'><B>Pinout Data:</B></TD>
 
<TD COLSPAN='2'><A HREF_DISABLED='D:/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\spi_master_atlys_top_par.xrpt?&DataKey=PinoutData'>Pinout Report</A></TD>
 
</TR>
 
<TR ALIGN=LEFT>
 
<TD BGCOLOR='#FFFF99'><B>Routing Results:</B></TD><TD>
 
All Signals Completely Routed</TD>
 
<TD BGCOLOR='#FFFF99'><B>Clock Data:</B></TD>
 
<TD COLSPAN='2'><A HREF_DISABLED='D:/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\spi_master_atlys_top_par.xrpt?&DataKey=ClocksData'>Clock Report</A></TD>
 
</TR>
 
<TR ALIGN=LEFT>
 
<TD BGCOLOR='#FFFF99'><B>Timing Constraints:</B></TD>
 
<TD>
 
<A HREF_DISABLED='D:/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\spi_master_atlys_top.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD>
 
<TD BGCOLOR='#FFFF99'><B>&nbsp;</B></TD>
 
<TD COLSPAN='2'>&nbsp;</TD>
 
</TABLE>
 
 
 
 
 
 
 
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='D:/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\spi_master_atlys_top.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>qua 10. ago 22:56:21 2011</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spimasterslave/spi_master_slave/trunk/syn\spi_master_atlys_top.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Sun Aug 28 23:35:13 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spimasterslave/spi_master_slave/trunk/syn\_xmsgs/xst.xmsgs?&DataKey=Warning'>28 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spimasterslave/spi_master_slave/trunk/syn\_xmsgs/xst.xmsgs?&DataKey=Info'>24 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD>Translation Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spimasterslave/spi_master_slave/trunk/syn\spi_master_atlys_top.bld'>Translation Report</A></TD><TD>Out of Date</TD><TD>Sun Aug 28 23:23:42 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='D:/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\spi_master_atlys_top_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>qua 10. ago 22:56:49 2011</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spimasterslave/spi_master_slave/trunk/syn\spi_master_atlys_top_map.mrp'>Map Report</A></TD><TD>Out of Date</TD><TD>Sun Aug 28 23:24:01 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spimasterslave/spi_master_slave/trunk/syn\_xmsgs/map.xmsgs?&DataKey=Info'>13 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='D:/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\spi_master_atlys_top.par'>Place and Route Report</A></TD><TD>Current</TD><TD>qua 10. ago 22:57:01 2011</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spimasterslave/spi_master_slave/trunk/syn\spi_master_atlys_top.par'>Place and Route Report</A></TD><TD>Out of Date</TD><TD>Sun Aug 28 23:24:13 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spimasterslave/spi_master_slave/trunk/syn\_xmsgs/par.xmsgs?&DataKey=Warning'>1 Warning (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spimasterslave/spi_master_slave/trunk/syn\_xmsgs/par.xmsgs?&DataKey=Info'>4 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='D:/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\spi_master_atlys_top.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>qua 10. ago 22:57:08 2011</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spimasterslave/spi_master_slave/trunk/syn\spi_master_atlys_top.twr'>Post-PAR Static Timing Report</A></TD><TD>Out of Date</TD><TD>Sun Aug 28 23:24:19 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spimasterslave/spi_master_slave/trunk/syn\_xmsgs/trce.xmsgs?&DataKey=Info'>3 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
</TABLE>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='D:/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\spi_master_atlys_top_map.psr'>Physical Synthesis Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>qua 10. ago 22:56:49 2011</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spimasterslave/spi_master_slave/trunk/syn\isim.log'>ISIM Simulator Log</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Sun Aug 28 23:30:20 2011</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='D:/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>qua 10. ago 22:59:16 2011</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spimasterslave/spi_master_slave/trunk/syn\netgen/synthesis/spi_master_atlys_top_synthesis.nlf'>Post-Synthesis Simulation Model Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Sun Aug 28 23:19:42 2011</TD></TR>
 
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spimasterslave/spi_master_slave/trunk/syn\netgen/translate/spi_master_atlys_top_translate.nlf'>Post-Translate Simulation Model Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Sun Aug 28 23:19:45 2011</TD></TR>
 
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spimasterslave/spi_master_slave/trunk/syn\netgen/map/spi_master_atlys_top_map.nlf'>Post-Map Simulation Model Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Sun Aug 28 23:20:15 2011</TD></TR>
 
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spimasterslave/spi_master_slave/trunk/syn\spi_master_atlys_top_map.psr'>Physical Synthesis Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Sun Aug 28 23:24:01 2011</TD></TR>
 
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spimasterslave/spi_master_slave/trunk/syn\netgen/par/spi_master_atlys_top_timesim.nlf'>Post-Place and Route Simulation Model Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Sun Aug 28 23:24:26 2011</TD></TR>
 
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spimasterslave/spi_master_slave/trunk/syn\usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Wed Aug 10 23:31:06 2011</TD></TR>
</TABLE>
</TABLE>
 
 
 
 
<br><center><b>Date Generated:</b> 08/11/2011 - 18:45:24</center>
<br><center><b>Date Generated:</b> 08/28/2011 - 23:44:54</center>
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