| Line 118... |
Line 118... |
-- 2011/08/01 v2.01.0115 [JD] Adjusted 'do_valid_o' pulse width to be 2 'clk_i', as in the master core.
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-- 2011/08/01 v2.01.0115 [JD] Adjusted 'do_valid_o' pulse width to be 2 'clk_i', as in the master core.
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-- Simulated in iSim with the master core for continuous transmission mode.
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-- Simulated in iSim with the master core for continuous transmission mode.
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-- 2011/08/02 v2.02.0120 [JD] Added mux for MISO at reset state, to output di(N-1) at start. This fixed a bug in first bit.
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-- 2011/08/02 v2.02.0120 [JD] Added mux for MISO at reset state, to output di(N-1) at start. This fixed a bug in first bit.
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-- The master and slave cores were verified in FPGA with continuous transmission, for all SPI modes.
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-- The master and slave cores were verified in FPGA with continuous transmission, for all SPI modes.
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-- 2011/08/04 v2.02.0121 [JD] Changed minor comment bugs in the combinatorial fsm logic.
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-- 2011/08/04 v2.02.0121 [JD] Changed minor comment bugs in the combinatorial fsm logic.
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-- 2011/08/08 v2.02.0122 [JD] FIX: continuous transfer mode bug. When wren_i is not strobed prior to state 1 (last bit), the
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-- sequencer goes to state 0, and then to state 'N' again. This produces a wrong bit-shift for received
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-- data. The fix consists in engaging continuous transfer regardless of the user strobing write enable, and
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-- sequencing from state 1 to N as long as the master clock is present. If the user does not write new
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-- data, the last data word is repeated.
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--
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--
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--
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--
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-----------------------------------------------------------------------------------------------------------------------
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-----------------------------------------------------------------------------------------------------------------------
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-- TODO
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-- TODO
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-- ====
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-- ====
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Line 380... |
when 1 => -- transfer rx data to do_buffer and restart if new data is written
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when 1 => -- transfer rx data to do_buffer and restart if new data is written
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sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb
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sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb
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sh_next(N-1 downto 1) <= di_reg(N-2 downto 0); -- shift inner bits
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sh_next(N-1 downto 1) <= di_reg(N-2 downto 0); -- shift inner bits
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tx_bit_next <= di_reg(N-1); -- first output bit comes from the MSb of parallel data
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tx_bit_next <= di_reg(N-1); -- first output bit comes from the MSb of parallel data
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di_req_next <= '0'; -- prefetch data request: deassert when shifting data
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di_req_next <= '0'; -- prefetch data request: deassert when shifting data
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state_next <= N; -- next state is top bit of new data
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if wren = '1' then -- load tx register if valid data present at di_reg
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if wren = '1' then -- load tx register if valid data present at di_reg
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wr_ack_next <= '1'; -- acknowledge data in transfer
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wr_ack_next <= '1'; -- acknowledge data in transfer
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state_next <= N; -- next state is top bit of new data
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else
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else
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wr_ack_next <= '0'; -- remove data load ack for all but the load stages
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wr_ack_next <= '0'; -- remove data load ack for all but the load stages
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sh_next <= (others => '0'); -- load null data (output '0' if no load)
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state_next <= 0; -- next state is idle state
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end if;
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end if;
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when 0 => -- idle state: start and end of transmission
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when 0 => -- idle state: start and end of transmission
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sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb
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sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb
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sh_next(N-1 downto 1) <= di_reg(N-2 downto 0); -- shift inner bits
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sh_next(N-1 downto 1) <= di_reg(N-2 downto 0); -- shift inner bits
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