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[/] [suslik/] [branches/] [tlb/] [arch.txt] - Diff between revs 2 and 5
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Rev 5 |
imm is either 16 bit sign extended or full 32 bit with prefix instr(except andi1)
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imm is either 16 bit sign extended or full 32 bit with prefix instr(except andi1)
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there are 32 registers
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there are 32 registers
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alu instructions have 6-bit opcode(lowest 6 bits), shared with conditional jumps and load/store and call
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alu instructions have 6-bit opcode(lowest 6 bits), shared with conditional jumps and load/store and call
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2 opcodes reserved for future 64bitload&store (59 & 63)
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2 opcodes reserved for future 64bitload&store (59 & 63)
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not shared with in/out
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not shared with in/out
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no condition flags exist in this architecture so far, instead, use compare-and-jump
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no condition flags exist in this architecture so far, instead, use compare-and-jump
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opcode 32 is used for i/o and system instructions, using the other bits
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opcode 32 is used for i/o and system instructions, using the other bits
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i/o instructions have additional opcode at bits 26:21, but this can be used for system
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i/o instructions have additional opcode at bits 26:21, but this can be used for system
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instructions also.
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instructions also.
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opcode 30 prefix imm
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opcode 30 prefix imm
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opcode 0
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opcode 0
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lih reg1,imm,reg2
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lih reg1,imm,reg2
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lch reg1,imm,reg2 //equivalent
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lch reg1,imm,reg2 //equivalent
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store imm into upper half of reg2, reg1's lower half into lower half of reg2
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store imm into upper half of reg2, reg1's lower half into lower half of reg2
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opcode 1
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opcode 1
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li imm,reg
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li imm,reg
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lc imm,reg
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lc imm,reg
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store imm into reg
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store imm into reg
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opcode 2
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opcode 2
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and reg1,reg2,reg2
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and reg1,reg2,reg2
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reg2=reg1®2
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reg2=reg1®2
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opcode 3
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opcode 3
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andi reg1,imm,reg2
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andi reg1,imm,reg2
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reg2=reg1&imm
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reg2=reg1&imm
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opcode 4
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opcode 4
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or reg1,reg2,reg3
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or reg1,reg2,reg3
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reg3=reg1|reg2
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reg3=reg1|reg2
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opcode 5
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opcode 5
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ori reg1,imm,reg
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ori reg1,imm,reg
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reg2=reg1|imm
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reg2=reg1|imm
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opcode 6
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opcode 6
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xor reg1,reg2,reg3
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xor reg1,reg2,reg3
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reg3=reg1^reg2
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reg3=reg1^reg2
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opcode 7
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opcode 7
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xori reg1,imm,reg2
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xori reg1,imm,reg2
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reg2=imm^reg1
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reg2=imm^reg1
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opcode 8
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opcode 8
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add reg1,reg2,reg3
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add reg1,reg2,reg3
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reg3=reg1+reg2
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reg3=reg1+reg2
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opcode 9
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opcode 9
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addi reg1,imm,reg2
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addi reg1,imm,reg2
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reg2=reg1+imm
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reg2=reg1+imm
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opcode 10
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opcode 10
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sub reg1,reg2,reg3
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sub reg1,reg2,reg3
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reg3=reg1-reg2
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reg3=reg1-reg2
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opcode 11
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opcode 11
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subi reg1,imm,reg2
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subi reg1,imm,reg2
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reg2=reg1-imm
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reg2=reg1-imm
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opcode 12
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opcode 12
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nop
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nop
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no operation
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no operation
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opcode 13
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opcode 13
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andi1 reg1,imm,reg2
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andi1 reg1,imm,reg2
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reg2=reg1 & imm(one extended)
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reg2=reg1 & imm(one extended)
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shl reg1,reg2,reg3
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shl reg1,reg2,reg3
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shli reg1,imm,reg2
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shli reg1,imm,reg2
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shr reg1,reg2,
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shr reg1,reg2,
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reg3
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reg3
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shri reg1,imm,reg2
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shri reg1,imm,reg2
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sar reg1,reg2,reg3
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sar reg1,reg2,reg3
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sari reg1,imm,reg2
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sari reg1,imm,reg2
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inb r1,r2
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inb r1,r2
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inw r1,r2
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inw r1,r2
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inl r1,r2
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inl r1,r2
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outb r1,r2
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outb r1,r2
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outw r1,r2
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outw r1,r2
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outl r1,r2
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outl r1,r2
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conditional jumps
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conditional jumps
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cjule r1,r2, label
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cjule r1,r2, label
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cjc r1,r2, label
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cjc r1,r2, label
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cjugt r1,r2, label
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cjugt r1,r2, label
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cjnc r1,r2, label
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cjnc r1,r2, label
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cjeq r1,r2, label
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cjeq r1,r2, label
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cjne r1,r2, label
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cjne r1,r2, label
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cjult r1,r2, label
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cjult r1,r2, label
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cjuge r1,r2, label
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cjuge r1,r2, label
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cjn r1,r2, label
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cjn r1,r2, label
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cjnn r1,r2, label
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cjnn r1,r2, label
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cjslt r1,r2, label
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cjslt r1,r2, label
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cjsge r1,r2, label
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cjsge r1,r2, label
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cjsle r1,r2, label
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cjsle r1,r2, label
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cjsgt r1,r2, label
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cjsgt r1,r2, label
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cjo r1,r2, label
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cjo r1,r2, label
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cjno r1,r2, label
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cjno r1,r2, label
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call r1,imm,r2
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call r1,imm,r2
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call (r1+imm) return addr=r2
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call (r1+imm) return addr=r2
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ret r1
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ret r1
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ldl r1,imm/label,r2
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ldl r1,imm/label,r2
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ldw r1,imm/label,r2
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ldw r1,imm/label,r2
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ldb r1,imm/label,r2
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ldb r1,imm/label,r2
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stl r1,imm/label,r2
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stl r1,imm/label,r2
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stw r1,imm/label,r2
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stw r1,imm/label,r2
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stb r1,imm/label,r2
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stb r1,imm/label,r2
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