| Line 1... |
Line 1... |
`include "config.v"
|
`include "config.v"
|
|
|
module datacache(input clk,input stall,input [4:0] stginhibit,input [4:0] codemiss,input [31:0] addrA,output `muxnet [511:0] dataA,input [511:0] cacheLine,input [31:0] writeData,output `muxnet cacheHit,input readen,input writeen,input insert,input initEntry,input [1:0] readsz,output `muxnet [31:0] oldAddr);
|
module datacache(
|
|
input clk,
|
|
input stall,
|
|
input [4:0] stginhibit,
|
|
input [4:0] codemiss,
|
|
input [31:0] addrA,
|
|
output wire [511:0] dataA,
|
|
input [511:0] cacheLine,
|
|
input [31:0] writeData,
|
|
output wire cacheHit,
|
|
input readen,
|
|
input writeen,
|
|
input insert,
|
|
input initEntry,
|
|
input [1:0] readsz,
|
|
output wire [31:0] oldAddr);
|
|
|
wire tagwe;
|
wire tagwe;
|
wire [31:0] tagAddrA;
|
wire [31:0] tagAddrA;
|
wire [31:0] tagAddrW;
|
wire [31:0] tagAddrW;
|
wire [119:0] tagDataA;
|
wire [119:0] tagDataA;
|
`muxnet [119:0] tagDataW;
|
wire [119:0] tagDataW;
|
reg [31:0] tagAddrA_reg;
|
reg [31:0] tagAddrA_reg;
|
|
|
reg readen_reg=0;
|
reg readen_reg=0;
|
reg writeen_reg=0;
|
reg writeen_reg=0;
|
reg insert_reg=0;
|
reg insert_reg=0;
|
| Line 37... |
Line 52... |
wire [1:0] newPos0;
|
wire [1:0] newPos0;
|
wire [1:0] newPos1;
|
wire [1:0] newPos1;
|
wire [1:0] newPos2;
|
wire [1:0] newPos2;
|
wire [1:0] newPos3;
|
wire [1:0] newPos3;
|
|
|
`muxnet hit3,hit2,hit1,hit0;
|
wire hit3,hit2,hit1,hit0;
|
wire hit;
|
wire hit;
|
|
|
wire ram0We,ram1We,ram2We,ram3We;
|
wire ram0We,ram1We,ram2We,ram3We;
|
wire [31:0] ramAddrW;
|
wire [31:0] ramAddrW;
|
wire [31:0] ramAddrA;
|
wire [31:0] ramAddrA;
|
| Line 94... |
Line 109... |
assign pad3[5:0]=6'b0;
|
assign pad3[5:0]=6'b0;
|
assign pad2[5:0]=6'b0;
|
assign pad2[5:0]=6'b0;
|
assign pad1[5:0]=6'b0;
|
assign pad1[5:0]=6'b0;
|
assign pad0[5:0]=6'b0;
|
assign pad0[5:0]=6'b0;
|
|
|
assign hit3=(readen_reg || writeen_reg) ? val3 && (pad3[31:6]==tagAddrA_reg[31:6]) : 1'b`muxval;
|
assign hit3=(readen_reg || writeen_reg) ? val3 && (pad3[31:6]==tagAddrA_reg[31:6]) : 1'bz;
|
assign hit2=(readen_reg || writeen_reg) ? val2 && (pad2[31:6]==tagAddrA_reg[31:6]) : 1'b`muxval;
|
assign hit2=(readen_reg || writeen_reg) ? val2 && (pad2[31:6]==tagAddrA_reg[31:6]) : 1'bz;
|
assign hit1=(readen_reg || writeen_reg) ? val1 && (pad1[31:6]==tagAddrA_reg[31:6]) : 1'b`muxval;
|
assign hit1=(readen_reg || writeen_reg) ? val1 && (pad1[31:6]==tagAddrA_reg[31:6]) : 1'bz;
|
assign hit0=(readen_reg || writeen_reg) ? val0 && (pad0[31:6]==tagAddrA_reg[31:6]) : 1'b`muxval;
|
assign hit0=(readen_reg || writeen_reg) ? val0 && (pad0[31:6]==tagAddrA_reg[31:6]) : 1'bz;
|
|
|
assign hit3=insert_reg ? (pos3==2'b11) : 1'b`muxval;
|
assign hit3=insert_reg ? (pos3==2'b11) : 1'bz;
|
assign hit2=insert_reg ? (pos2==2'b11) : 1'b`muxval;
|
assign hit2=insert_reg ? (pos2==2'b11) : 1'bz;
|
assign hit1=insert_reg ? (pos1==2'b11) : 1'b`muxval;
|
assign hit1=insert_reg ? (pos1==2'b11) : 1'bz;
|
assign hit0=insert_reg ? (pos0==2'b11) : 1'b`muxval;
|
assign hit0=insert_reg ? (pos0==2'b11) : 1'bz;
|
|
|
assign hit3=(!insert_reg && !readen_reg && !writeen_reg) ? 1'b0 : 1'b`muxval;
|
assign hit3=(!insert_reg && !readen_reg && !writeen_reg) ? 1'b0 : 1'bz;
|
assign hit2=(!insert_reg && !readen_reg && !writeen_reg) ? 1'b0 : 1'b`muxval;
|
assign hit2=(!insert_reg && !readen_reg && !writeen_reg) ? 1'b0 : 1'bz;
|
assign hit1=(!insert_reg && !readen_reg && !writeen_reg) ? 1'b0 : 1'b`muxval;
|
assign hit1=(!insert_reg && !readen_reg && !writeen_reg) ? 1'b0 : 1'bz;
|
assign hit0=(!insert_reg && !readen_reg && !writeen_reg) ? 1'b0 : 1'b`muxval;
|
assign hit0=(!insert_reg && !readen_reg && !writeen_reg) ? 1'b0 : 1'bz;
|
|
|
assign hit=hit3 || hit2 || hit1 || hit0;
|
assign hit=hit3 || hit2 || hit1 || hit0;
|
|
|
assign cacheHit= (insert_reg && hit0) ? val0 && dir0 : 1'b`muxval;
|
assign cacheHit= (insert_reg && hit0) ? val0 && dir0 : 1'bz;
|
assign cacheHit= (insert_reg && hit1) ? val1 && dir1 : 1'b`muxval;
|
assign cacheHit= (insert_reg && hit1) ? val1 && dir1 : 1'bz;
|
assign cacheHit= (insert_reg && hit2) ? val2 && dir2 : 1'b`muxval;
|
assign cacheHit= (insert_reg && hit2) ? val2 && dir2 : 1'bz;
|
assign cacheHit= (insert_reg && hit3) ? val3 && dir3 : 1'b`muxval;
|
assign cacheHit= (insert_reg && hit3) ? val3 && dir3 : 1'bz;
|
assign cacheHit= insert_reg ? 1'b`muxval : hit;
|
assign cacheHit= insert_reg ? 1'bz : hit;
|
|
|
assign tagDataW=readen_reg ? { pad3[31:6],pad2[31:6],pad1[31:6],pad0[31:6],
|
assign tagDataW=readen_reg ? { pad3[31:6],pad2[31:6],pad1[31:6],pad0[31:6],
|
newPos3,newPos2,newPos1,newPos0,
|
newPos3,newPos2,newPos1,newPos0,
|
val3,val2,val1,val0,
|
val3,val2,val1,val0,
|
dir3,dir2,dir1,dir0 } : 120'b`muxval;
|
dir3,dir2,dir1,dir0 } : 120'bz;
|
assign tagDataW=(writeen_reg && hit0) ? { pad3[31:6],pad2[31:6],pad1[31:6],pad0[31:6],
|
assign tagDataW=(writeen_reg && hit0) ? { pad3[31:6],pad2[31:6],pad1[31:6],pad0[31:6],
|
newPos3,newPos2,newPos1,newPos0,
|
newPos3,newPos2,newPos1,newPos0,
|
val3,val2,val1,val0,
|
val3,val2,val1,val0,
|
dir3,dir2,dir1,1'b1 } : 120'b`muxval;
|
dir3,dir2,dir1,1'b1 } : 120'bz;
|
assign tagDataW=(writeen_reg && hit1) ? { pad3[31:6],pad2[31:6],pad1[31:6],pad0[31:6],
|
assign tagDataW=(writeen_reg && hit1) ? { pad3[31:6],pad2[31:6],pad1[31:6],pad0[31:6],
|
newPos3,newPos2,newPos1,newPos0,
|
newPos3,newPos2,newPos1,newPos0,
|
val3,val2,val1,val0,
|
val3,val2,val1,val0,
|
dir3,dir2,1'b1,dir0 } : 120'b`muxval;
|
dir3,dir2,1'b1,dir0 } : 120'bz;
|
assign tagDataW=(writeen_reg && hit2) ? { pad3[31:6],pad2[31:6],pad1[31:6],pad0[31:6],
|
assign tagDataW=(writeen_reg && hit2) ? { pad3[31:6],pad2[31:6],pad1[31:6],pad0[31:6],
|
newPos3,newPos2,newPos1,newPos0,
|
newPos3,newPos2,newPos1,newPos0,
|
val3,val2,val1,val0,
|
val3,val2,val1,val0,
|
dir3,1'b1,dir1,dir0 } : 120'b`muxval;
|
dir3,1'b1,dir1,dir0 } : 120'bz;
|
assign tagDataW=(writeen_reg && hit3) ? { pad3[31:6],pad2[31:6],pad1[31:6],pad0[31:6],
|
assign tagDataW=(writeen_reg && hit3) ? { pad3[31:6],pad2[31:6],pad1[31:6],pad0[31:6],
|
newPos3,newPos2,newPos1,newPos0,
|
newPos3,newPos2,newPos1,newPos0,
|
val3,val2,val1,val0,
|
val3,val2,val1,val0,
|
1'b1,dir2,dir1,dir0 } : 120'b`muxval;
|
1'b1,dir2,dir1,dir0 } : 120'bz;
|
assign tagDataW=(writeen_reg && !hit) ? { pad3[31:6],pad2[31:6],pad1[31:6],pad0[31:6],
|
assign tagDataW=(writeen_reg && !hit) ? { pad3[31:6],pad2[31:6],pad1[31:6],pad0[31:6],
|
newPos3,newPos2,newPos1,newPos0,
|
newPos3,newPos2,newPos1,newPos0,
|
val3,val2,val1,val0,
|
val3,val2,val1,val0,
|
dir3,dir2,dir1,dir0 } : 120'b`muxval;
|
dir3,dir2,dir1,dir0 } : 120'bz;
|
|
|
assign tagDataW=(insert_reg && hit0) ? { pad3[31:6],pad2[31:6],pad1[31:6],tagAddrA_reg[31:6],
|
assign tagDataW=(insert_reg && hit0) ? { pad3[31:6],pad2[31:6],pad1[31:6],tagAddrA_reg[31:6],
|
newPos3,newPos2,newPos1,newPos0,
|
newPos3,newPos2,newPos1,newPos0,
|
val3,val2,val1,1'b1,
|
val3,val2,val1,1'b1,
|
dir3,dir2,dir1,1'b0 } : 120'b`muxval;
|
dir3,dir2,dir1,1'b0 } : 120'bz;
|
assign tagDataW=(insert_reg && hit1) ? { pad3[31:6],pad2[31:6],tagAddrA_reg[31:6],pad0[31:6],
|
assign tagDataW=(insert_reg && hit1) ? { pad3[31:6],pad2[31:6],tagAddrA_reg[31:6],pad0[31:6],
|
newPos3,newPos2,newPos1,newPos0,
|
newPos3,newPos2,newPos1,newPos0,
|
val3,val2,1'b1,val0,
|
val3,val2,1'b1,val0,
|
dir3,dir2,1'b0,dir0 } : 120'b`muxval;
|
dir3,dir2,1'b0,dir0 } : 120'bz;
|
assign tagDataW=(insert_reg && hit2) ? { pad3[31:6],tagAddrA_reg[31:6],pad1[31:6],pad0[31:6],
|
assign tagDataW=(insert_reg && hit2) ? { pad3[31:6],tagAddrA_reg[31:6],pad1[31:6],pad0[31:6],
|
newPos3,newPos2,newPos1,newPos0,
|
newPos3,newPos2,newPos1,newPos0,
|
val3,1'b1,val1,val0,
|
val3,1'b1,val1,val0,
|
dir3,1'b0,dir1,dir0 } : 120'b`muxval;
|
dir3,1'b0,dir1,dir0 } : 120'bz;
|
assign tagDataW=(insert_reg && hit3) ? { tagAddrA_reg[31:6],pad2[31:6],pad1[31:6],pad0[31:6],
|
assign tagDataW=(insert_reg && hit3) ? { tagAddrA_reg[31:6],pad2[31:6],pad1[31:6],pad0[31:6],
|
newPos3,newPos2,newPos1,newPos0,
|
newPos3,newPos2,newPos1,newPos0,
|
1'b1,val2,val1,val0,
|
1'b1,val2,val1,val0,
|
1'b0,dir2,dir1,dir0 } : 120'b`muxval;
|
1'b0,dir2,dir1,dir0 } : 120'bz;
|
// assign tagDataW=(insert_reg && !hit) ? 120'b0 : 120'bz;
|
// assign tagDataW=(insert_reg && !hit) ? 120'b0 : 120'bz;
|
assign tagDataW=initEntry_reg ? { 26'b0,26'b0,26'b0,26'b0,
|
assign tagDataW=initEntry_reg ? { 26'b0,26'b0,26'b0,26'b0,
|
2'b11,2'b10,2'b01,2'b00,
|
2'b11,2'b10,2'b01,2'b00,
|
1'b0,1'b0,1'b0,1'b0,
|
1'b0,1'b0,1'b0,1'b0,
|
1'b0,1'b0,1'b0,1'b0} : 120'b`muxval;
|
1'b0,1'b0,1'b0,1'b0} : 120'bz;
|
assign tagDataW=(!insert_reg && !readen_reg && !writeen_reg && !initEntry_reg) ? 120'b0 : 120'b`muxval;
|
assign tagDataW=(!insert_reg && !readen_reg && !writeen_reg && !initEntry_reg) ? 120'b0 : 120'bz;
|
|
|
assign dataA=(!insert_reg && hit0) ? {480'b0,dataA0} : 512'b`muxval;
|
assign dataA=(!insert_reg && hit0) ? {480'b0,dataA0} : 512'bz;
|
assign dataA=(!insert_reg && hit1) ? {480'b0,dataA1} : 512'b`muxval;
|
assign dataA=(!insert_reg && hit1) ? {480'b0,dataA1} : 512'bz;
|
assign dataA=(!insert_reg && hit2) ? {480'b0,dataA2} : 512'b`muxval;
|
assign dataA=(!insert_reg && hit2) ? {480'b0,dataA2} : 512'bz;
|
|
|
assign dataA=(!insert_reg && hit3) ? {480'b0,dataA3} : 512'b`muxval;
|
assign dataA=(!insert_reg && hit3) ? {480'b0,dataA3} : 512'bz;
|
|
|
assign dataA=(insert_reg && hit0) ? ramDataR0 : 512'b`muxval;
|
assign dataA=(insert_reg && hit0) ? ramDataR0 : 512'bz;
|
|
|
assign dataA=(insert_reg && hit1) ? ramDataR1 : 512'b`muxval;
|
assign dataA=(insert_reg && hit1) ? ramDataR1 : 512'bz;
|
assign dataA=(insert_reg && hit2) ? ramDataR2 : 512'b`muxval;
|
assign dataA=(insert_reg && hit2) ? ramDataR2 : 512'bz;
|
assign dataA=(insert_reg && hit3) ? ramDataR3 : 512'b`muxval;
|
assign dataA=(insert_reg && hit3) ? ramDataR3 : 512'bz;
|
|
|
assign dataA= hit ? 512'b`muxval : 512'b0; //change to accomodate non-read ops
|
assign dataA= hit ? 512'bz : 512'b0; //change to accomodate non-read ops
|
|
|
assign ramDataW0=insert_reg ? cacheLine_reg : ramDataWA0;
|
assign ramDataW0=insert_reg ? cacheLine_reg : ramDataWA0;
|
assign ramDataW1=insert_reg ? cacheLine_reg : ramDataWA1;
|
assign ramDataW1=insert_reg ? cacheLine_reg : ramDataWA1;
|
assign ramDataW2=insert_reg ? cacheLine_reg : ramDataWA2;
|
assign ramDataW2=insert_reg ? cacheLine_reg : ramDataWA2;
|
assign ramDataW3=insert_reg ? cacheLine_reg : ramDataWA3;
|
assign ramDataW3=insert_reg ? cacheLine_reg : ramDataWA3;
|
| Line 189... |
Line 204... |
assign ram0We=(insert_reg || (writeen_reg && !stall && !codemiss[4] && !stginhibit[4])) && hit0;
|
assign ram0We=(insert_reg || (writeen_reg && !stall && !codemiss[4] && !stginhibit[4])) && hit0;
|
assign ram1We=(insert_reg || (writeen_reg && !stall && !codemiss[4] && !stginhibit[4])) && hit1;
|
assign ram1We=(insert_reg || (writeen_reg && !stall && !codemiss[4] && !stginhibit[4])) && hit1;
|
assign ram2We=(insert_reg || (writeen_reg && !stall && !codemiss[4] && !stginhibit[4])) && hit2;
|
assign ram2We=(insert_reg || (writeen_reg && !stall && !codemiss[4] && !stginhibit[4])) && hit2;
|
assign ram3We=(insert_reg || (writeen_reg && !stall && !codemiss[4] && !stginhibit[4])) && hit3;
|
assign ram3We=(insert_reg || (writeen_reg && !stall && !codemiss[4] && !stginhibit[4])) && hit3;
|
|
|
assign oldAddr=(insert_reg && hit0) ? pad0 : 32'b`muxval;
|
assign oldAddr=(insert_reg && hit0) ? pad0 : 32'bz;
|
assign oldAddr=(insert_reg && hit1) ? pad1 : 32'b`muxval;
|
assign oldAddr=(insert_reg && hit1) ? pad1 : 32'bz;
|
assign oldAddr=(insert_reg && hit2) ? pad2 : 32'b`muxval;
|
assign oldAddr=(insert_reg && hit2) ? pad2 : 32'bz;
|
assign oldAddr=(insert_reg && hit3) ? pad3 : 32'b`muxval;
|
assign oldAddr=(insert_reg && hit3) ? pad3 : 32'bz;
|
assign oldAddr=(!insert_reg) ? 32'b0 : 32'b`muxval;
|
assign oldAddr=(!insert_reg) ? 32'b0 : 32'bz;
|
|
|
assign ramAddrA={tagAddrA[31:6],6'b0};
|
assign ramAddrA={tagAddrA[31:6],6'b0};
|
assign ramAddrW={tagAddrA_reg[31:6],6'b0};
|
assign ramAddrW={tagAddrA_reg[31:6],6'b0};
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
| Line 270... |
Line 285... |
|
|
endmodule
|
endmodule
|
|
|
module datacache_get_new_pos(input [1:0] pos0,input [1:0] pos1,input [1:0] pos2,input [1:0] pos3,
|
module datacache_get_new_pos(input [1:0] pos0,input [1:0] pos1,input [1:0] pos2,input [1:0] pos3,
|
input hit0,input hit1,input hit2,input hit3,
|
input hit0,input hit1,input hit2,input hit3,
|
output `muxnet [1:0] newPos0,output `muxnet [1:0] newPos1,output `muxnet [1:0] newPos2,output `muxnet [1:0] newPos3);
|
output wire [1:0] newPos0,output wire [1:0] newPos1,output wire [1:0] newPos2,output wire [1:0] newPos3);
|
wire hit;
|
wire hit;
|
|
|
assign hit=hit0 || hit1 || hit2 || hit3;
|
assign hit=hit0 || hit1 || hit2 || hit3;
|
|
|
assign newPos0=hit0 ? 0 : 2'b`muxval;
|
assign newPos0=hit0 ? 0 : 2'bz;
|
assign newPos1=hit0 ? ((pos1<pos0) ? pos1+1:pos1 ) : 2'b`muxval;
|
assign newPos1=hit0 ? ((pos1<pos0) ? pos1+1:pos1 ) : 2'bz;
|
assign newPos2=hit0 ? ((pos2<pos0) ? pos2+1:pos2 ) : 2'b`muxval;
|
assign newPos2=hit0 ? ((pos2<pos0) ? pos2+1:pos2 ) : 2'bz;
|
assign newPos3=hit0 ? ((pos3<pos0) ? pos3+1:pos3 ) : 2'b`muxval;
|
assign newPos3=hit0 ? ((pos3<pos0) ? pos3+1:pos3 ) : 2'bz;
|
|
|
assign newPos1=hit1 ? 0 : 2'b`muxval;
|
assign newPos1=hit1 ? 0 : 2'bz;
|
assign newPos0=hit1 ? ((pos0<pos1) ? pos0+1:pos0 ) : 2'b`muxval;
|
assign newPos0=hit1 ? ((pos0<pos1) ? pos0+1:pos0 ) : 2'bz;
|
assign newPos2=hit1 ? ((pos2<pos1) ? pos2+1:pos2 ) : 2'b`muxval;
|
assign newPos2=hit1 ? ((pos2<pos1) ? pos2+1:pos2 ) : 2'bz;
|
assign newPos3=hit1 ? ((pos3<pos1) ? pos3+1:pos3 ) : 2'b`muxval;
|
assign newPos3=hit1 ? ((pos3<pos1) ? pos3+1:pos3 ) : 2'bz;
|
|
|
assign newPos2=hit2 ? 0 : 2'b`muxval;
|
assign newPos2=hit2 ? 0 : 2'bz;
|
assign newPos1=hit2 ? ((pos1<pos2) ? pos1+1:pos1 ) : 2'b`muxval;
|
assign newPos1=hit2 ? ((pos1<pos2) ? pos1+1:pos1 ) : 2'bz;
|
assign newPos0=hit2 ? ((pos0<pos2) ? pos0+1:pos0 ) : 2'b`muxval;
|
assign newPos0=hit2 ? ((pos0<pos2) ? pos0+1:pos0 ) : 2'bz;
|
assign newPos3=hit2 ? ((pos3<pos2) ? pos3+1:pos3 ) : 2'b`muxval;
|
assign newPos3=hit2 ? ((pos3<pos2) ? pos3+1:pos3 ) : 2'bz;
|
|
|
assign newPos3=hit3 ? 0 : 2'b`muxval;
|
assign newPos3=hit3 ? 0 : 2'bz;
|
assign newPos1=hit3 ? ((pos1<pos3) ? pos1+1:pos1 ) : 2'b`muxval;
|
assign newPos1=hit3 ? ((pos1<pos3) ? pos1+1:pos1 ) : 2'bz;
|
assign newPos2=hit3 ? ((pos2<pos3) ? pos2+1:pos2 ) : 2'b`muxval;
|
assign newPos2=hit3 ? ((pos2<pos3) ? pos2+1:pos2 ) : 2'bz;
|
assign newPos0=hit3 ? ((pos0<pos3) ? pos0+1:pos0 ) : 2'b`muxval;
|
assign newPos0=hit3 ? ((pos0<pos3) ? pos0+1:pos0 ) : 2'bz;
|
|
|
assign newPos0=hit ? 2'b`muxval : pos0;
|
assign newPos0=hit ? 2'bz : pos0;
|
assign newPos1=hit ? 2'b`muxval : pos1;
|
assign newPos1=hit ? 2'bz : pos1;
|
assign newPos2=hit ? 2'b`muxval : pos2;
|
assign newPos2=hit ? 2'bz : pos2;
|
assign newPos3=hit ? 2'b`muxval : pos3;
|
assign newPos3=hit ? 2'bz : pos3;
|
|
|
endmodule
|
endmodule
|
|
|
|
|
module datacache_data_sel(input [511:0] dataIn,input [5:0] sel, input [1:0] readsz, output `muxnet [31:0] dataOut);
|
module datacache_data_sel(input [511:0] dataIn,input [5:0] sel, input [1:0] readsz, output wire [31:0] dataOut);
|
wire [255:0] bit5Data;
|
wire [255:0] bit5Data;
|
wire [127:0] bit4Data;
|
wire [127:0] bit4Data;
|
wire [63:0] bit3Data;
|
wire [63:0] bit3Data;
|
wire [31:0] data32;
|
wire [31:0] data32;
|
wire [15:0] data16;
|
wire [15:0] data16;
|
| Line 319... |
Line 334... |
|
|
assign data32 =sel[2] ? bit3Data[63:32] : bit3Data[31:0];
|
assign data32 =sel[2] ? bit3Data[63:32] : bit3Data[31:0];
|
assign data16 =sel[1] ? data32[31:16] : data32[15:0];
|
assign data16 =sel[1] ? data32[31:16] : data32[15:0];
|
assign data8 =sel[0] ? data16[15:8] : data16[7:0];
|
assign data8 =sel[0] ? data16[15:8] : data16[7:0];
|
|
|
assign dataOut=(readsz==0) ? {24'b0,data8} : 32'b`muxval;
|
assign dataOut=(readsz==0) ? {24'b0,data8} : 32'bz;
|
assign dataOut=(readsz==1) ? {16'b0,data16} : 32'b`muxval;
|
assign dataOut=(readsz==1) ? {16'b0,data16} : 32'bz;
|
assign dataOut=(readsz==2) ? data32 : 32'b`muxval;
|
assign dataOut=(readsz==2) ? data32 : 32'bz;
|
assign dataOut=(readsz==4) ? 32'b0 : 32'b`muxval;
|
assign dataOut=(readsz==4) ? 32'b0 : 32'bz;
|
|
|
endmodule
|
endmodule
|
|
|
|
|
module datacache_write_shift(input [31:0] dataIn,input [1:0] writesz,input [31:0] addr, output wire [511:0] dataOut, output wire [63:0] byteEnable);
|
module datacache_write_shift(input [31:0] dataIn,input [1:0] writesz,input [31:0] addr, output wire [511:0] dataOut, output wire [63:0] byteEnable);
|
`muxnet [511:0] data6;
|
wire [511:0] data6;
|
wire [511:0] data5;
|
wire [511:0] data5;
|
wire [511:0] data4;
|
wire [511:0] data4;
|
wire [511:0] data3;
|
wire [511:0] data3;
|
wire [511:0] data2;
|
wire [511:0] data2;
|
wire [511:0] data1;
|
wire [511:0] data1;
|
wire [511:0] data0;
|
wire [511:0] data0;
|
|
|
`muxnet [63:0] byteEnable6;
|
wire [63:0] byteEnable6;
|
wire [63:0] byteEnable5;
|
wire [63:0] byteEnable5;
|
wire [63:0] byteEnable4;
|
wire [63:0] byteEnable4;
|
wire [63:0] byteEnable3;
|
wire [63:0] byteEnable3;
|
wire [63:0] byteEnable2;
|
wire [63:0] byteEnable2;
|
wire [63:0] byteEnable1;
|
wire [63:0] byteEnable1;
|
wire [63:0] byteEnable0;
|
wire [63:0] byteEnable0;
|
|
|
// change data6 to explicit mux!
|
// change data6 to explicit mux!
|
assign data6=(writesz==0) ? {504'b0,dataIn[7:0]} : 512'b`muxval;
|
assign data6=(writesz==0) ? {504'b0,dataIn[7:0]} : 512'bz;
|
assign data6=(writesz==1) ? {496'b0,dataIn[15:0]} : 512'b`muxval;
|
assign data6=(writesz==1) ? {496'b0,dataIn[15:0]} : 512'bz;
|
assign data6=(writesz==2) ? {480'b0,dataIn} : 512'b`muxval;
|
assign data6=(writesz==2) ? {480'b0,dataIn} : 512'bz;
|
assign data6=(writesz==3) ? 512'b0 : 512'b`muxval;
|
assign data6=(writesz==3) ? 512'b0 : 512'bz;
|
|
|
assign data5=addr[5] ? { data6[255:0], 256'b0 }: data6;
|
assign data5=addr[5] ? { data6[255:0], 256'b0 }: data6;
|
assign data4=addr[4] ? { data5[383:0], 128'b0 }: data5;
|
assign data4=addr[4] ? { data5[383:0], 128'b0 }: data5;
|
assign data3=addr[3] ? { data4[447:0], 64'b0 }: data4;
|
assign data3=addr[3] ? { data4[447:0], 64'b0 }: data4;
|
assign data2=addr[2] ? { data3[479:0], 32'b0 }: data3;
|
assign data2=addr[2] ? { data3[479:0], 32'b0 }: data3;
|
assign data1=addr[1] ? { data2[495:0], 16'b0 }: data2;
|
assign data1=addr[1] ? { data2[495:0], 16'b0 }: data2;
|
assign data0=addr[0] ? { data1[503:0], 8'b0 }: data1;
|
assign data0=addr[0] ? { data1[503:0], 8'b0 }: data1;
|
|
|
assign dataOut=data0;
|
assign dataOut=data0;
|
//change byteEnable6 to explicit mux!
|
//change byteEnable6 to explicit mux!
|
assign byteEnable6=(writesz==0) ? 64'b0001 : 64'b`muxval;
|
assign byteEnable6=(writesz==0) ? 64'b0001 : 64'bz;
|
assign byteEnable6=(writesz==1) ? 64'b0011 : 64'b`muxval;
|
assign byteEnable6=(writesz==1) ? 64'b0011 : 64'bz;
|
assign byteEnable6=(writesz==2) ? 64'b1111 : 64'b`muxval;
|
assign byteEnable6=(writesz==2) ? 64'b1111 : 64'bz;
|
assign byteEnable6=(writesz==3) ? 64'b0000 : 64'b`muxval;
|
assign byteEnable6=(writesz==3) ? 64'b0000 : 64'bz;
|
|
|
assign byteEnable5=addr[5] ? { byteEnable6[31:0],32'b0 } : byteEnable6;
|
assign byteEnable5=addr[5] ? { byteEnable6[31:0],32'b0 } : byteEnable6;
|
assign byteEnable4=addr[4] ? { byteEnable5[47:0],16'b0 } : byteEnable5;
|
assign byteEnable4=addr[4] ? { byteEnable5[47:0],16'b0 } : byteEnable5;
|
assign byteEnable3=addr[3] ? { byteEnable4[55:0],8'b0 } : byteEnable4;
|
assign byteEnable3=addr[3] ? { byteEnable4[55:0],8'b0 } : byteEnable4;
|
assign byteEnable2=addr[2] ? { byteEnable3[59:0],4'b0 } : byteEnable3;
|
assign byteEnable2=addr[2] ? { byteEnable3[59:0],4'b0 } : byteEnable3;
|
