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[/] [suslik/] [trunk/] [rtl/] [cpu.v] - Diff between revs 2 and 8

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Rev 2 Rev 8
Line 1... Line 1...
 
 
module aluplus(instr, val1, val2, valres, wrtval, cjmpinstr,cjmp,const1,retaddr);
module aluplus(instr, val1, val2, valres, wrtval, cjmpinstr,cjmp,const1,retaddr,wrspec);
 
 
  input [31:0] instr, val1, val2;
  input [31:0] instr, val1, val2;
  output [31:0] valres;
  output [31:0] valres;
  output wire wrtval,cjmpinstr;
  output wire wrtval,cjmpinstr;
  output cjmp;
  output cjmp;
  input [31:0] const1;
  input [31:0] const1;
  input [31:0] retaddr;
  input [31:0] retaddr;
 
  output wrspec;
 
 
  wire [5:0] code;
  wire [5:0] code;
  wire [31:0] valcmp;
  wire [31:0] valcmp;
  wire CF,NF,VF,ZF;
  wire CF,NF,VF,ZF;
 
 
  /*
  /*
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  assign valres=(code==7) ? val1 ^ const1 : 32'bz;
  assign valres=(code==7) ? val1 ^ const1 : 32'bz;
  assign valres=(code==8) ? val1 + val2            : 32'bz;
  assign valres=(code==8) ? val1 + val2            : 32'bz;
  assign valres=(code==9) ? val1 + const1 : 32'bz;
  assign valres=(code==9) ? val1 + const1 : 32'bz;
  assign valres=(code==10)? val1 - val2            : 32'bz;
  assign valres=(code==10)? val1 - val2            : 32'bz;
  assign valres=(code==11)? val1 - const1 : 32'bz;
  assign valres=(code==11)? val1 - const1 : 32'bz;
  //12=no-op
  assign valres=wrspec ? val1 : 32'bz;
  assign valres=(code==13)? val1 & {16'b1111111111111111, const1[15:0]} : 32'bz;
  assign valres=(code==13)? val1 & {16'b1111111111111111, const1[15:0]} : 32'bz;
  assign valres=(code==46) ? retaddr : 32'bz;
  assign valres=(code==46) ? retaddr : 32'bz;
  assign valres=(code==14)? val1 << val2[5:0] : 32'bz;
  assign valres=(code==14)? val1 << val2[5:0] : 32'bz;
  assign valres=(code==15)? val1 << const1[5:0] : 32'bz;
  assign valres=(code==15)? val1 << const1[5:0] : 32'bz;
  assign valres=(code==16)? val1 >> val2[5:0] : 32'bz;
  assign valres=(code==16)? val1 >> val2[5:0] : 32'bz;
  assign valres=(code==17)? val1 >> const1[5:0] : 32'bz;
  assign valres=(code==17)? val1 >> const1[5:0] : 32'bz;
  assign valres=(code==18)? {32{val1[31]},val1} >> val2[5:0] : 32'bz;
  assign valres=(code==18)? {32{val1[31]},val1} >> val2[5:0] : 32'bz;
  assign valres=(code==19)? {32{val1[31]},val1} >> const1[5:0] : 32'bz;
  assign valres=(code==19)? {32{val1[31]},val1} >> const1[5:0] : 32'bz;
 
 
  assign valres=wrtval ? 32'bz : 32'b0;
  assign valres=wrtval | wrspec ? 32'bz : 32'b0;
 
 
  assign wrtval=((code<=11) || (code>=13 && code<=19) || (code==46));
  assign wrtval=((code<=11) || (code>=13 && code<=19) || (code==46));
 
  assign wrspec=(code==12) && (instr[15:6]=10'd1);
 
 
  //flags for compare &jump
  //flags for compare &jump
  assign {CF,valcmp}=val1 - val2;
  assign {CF,valcmp}=val1 - val2;
  assign NF=valcmp[31];
  assign NF=valcmp[31];
  assign ZF=(val1==val2);
  assign ZF=(val1==val2);
Line 283... Line 286...
endmodule
endmodule
 
 
module cpu(input clk,input busEnRead,input busEnWrite, input busDataReady, output wire busRead, output wire busWrite,output wire [31:0] busAddr,
module cpu(input clk,input busEnRead,input busEnWrite, input busDataReady, output wire busRead, output wire busWrite,output wire [31:0] busAddr,
              input [511:0] busInput,output wire [511:0] busOutput,
              input [511:0] busInput,output wire [511:0] busOutput,
              output wire [31:0] ioBusAddr,output wire [1:0] ioBusSize, output wire [31:0] ioBusOut, input [31:0] ioBusIn, input ioBusRdy,
              output wire [31:0] ioBusAddr,output wire [1:0] ioBusSize, output wire [31:0] ioBusOut, input [31:0] ioBusIn, input ioBusRdy,
              output wire ioBusWr,output wire ioBusRd,output wire [3:0] dummy);
              output wire ioBusWr,output wire ioBusRd,output wire [3:0] dummy, input [15:0] irq);
  wire [31:0] fetchaddr,fetchdata,readaddr,readdata;
  wire [31:0] fetchaddr,fetchdata,readaddr,readdata;
  reg [31:0] readaddr_reg;
  reg [31:0] readaddr_reg;
  reg [4:0] stginhibit=5'b11110;
  reg [4:0] stginhibit=5'b11110;
  reg [4:0] stginhibit_wrt;
  reg [4:0] stginhibit_wrt;
  reg [31:0] IP=32'b0,IP2,IP3,IP4,IP5,instr=0,instr4=0;
  reg [31:0] IP=32'b0,IP2,IP3,IP4,IP5,instr=0,instr4=0;
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  wire wasGlobalStall=multiCycleStall[4];
  wire wasGlobalStall=multiCycleStall[4];
  wire ioInstrWrtVal;
  wire ioInstrWrtVal;
  wire ioInstrDoStall;
  wire ioInstrDoStall;
  wire ioInstrKeepStalling;
  wire ioInstrKeepStalling;
 
 
 
  reg [15:0] irq_bits=16'b0;
 
  reg [31:0] irq_handler=32'hffff_fff0;
 
 
 
  wire wrspec;
 
 
  //dataunit data0(clk,stall,stginhibit,readaddr,readdata,agureadsz,agureaden,aguwriteen,opB);
  //dataunit data0(clk,stall,stginhibit,readaddr,readdata,agureadsz,agureaden,aguwriteen,opB);
  datacache datacache0(clk,stall,stginhibit,codeMiss,dcAddr,dcDataA,busInput,opB,dcHit,dcReadEn,dcWriteEn,dcInsert,dcInitEntry,agureadsz,dcOldAddr);
  datacache datacache0(clk,stall,stginhibit,codeMiss,dcAddr,dcDataA,busInput,opB,dcHit,dcReadEn,dcWriteEn,dcInsert,dcInitEntry,agureadsz,dcOldAddr);
  regfileint0 regf0(clk,intregwe,rA,rB,rC,rF,intregdataA,intregdataB,intregdataC,intregdataF);
  regfileint0 regf0(clk,intregwe,rA,rB,rC,rF,intregdataA,intregdataB,intregdataC,intregdataF);
  aluplus alu0(instr4,opA,opB,opF,aluwrtval,alucjmpinstr,alucjmp,constBits4,retAddr);
  aluplus alu0(instr4,opA,opB,opF,aluwrtval,alucjmpinstr,alucjmp,constBits4,retAddr,wrspec);
  ioinstr ioinstr0(clk,stall,stginhibit,instr4,opA,opB,ioInstrResult,wasGlobalStall,ioInstrWrtVal,ioInstrDoStall,ioInstrKeepStalling,
  ioinstr ioinstr0(clk,stall,stginhibit,instr4,opA,opB,ioInstrResult,wasGlobalStall,ioInstrWrtVal,ioInstrDoStall,ioInstrKeepStalling,
                   ioBusAddr,ioBusSize,ioBusOut,ioBusIn,ioBusRdy,ioBusWr,ioBusRd);
                   ioBusAddr,ioBusSize,ioBusOut,ioBusIn,ioBusRdy,ioBusWr,ioBusRd);
  subagu agu0(clk,stall,stginhibit,opC,instr0,instr,instr4,aguaddr,aguwrtval,agustall,agureadsz,agureaden,aguwriteen,constBits);
  subagu agu0(clk,stall,stginhibit,opC,instr0,instr,instr4,aguaddr,aguwrtval,agustall,agureadsz,agureaden,aguwriteen,constBits);
  brpred brpred0(clk,stall,stginhibit,fetchaddr,brpred_hit,brpred_instr,brpred_nextaddr,brpred_taken,
  brpred brpred0(clk,stall,stginhibit,fetchaddr,brpred_hit,brpred_instr,brpred_nextaddr,brpred_taken,
                 brpred_instertaddr,brpred_instertinstr,brpred_insertnextaddr,brpred_inserttaken,brpred_jumpinstr,brpred_addrMismatch);
                 brpred_instertaddr,brpred_instertinstr,brpred_insertnextaddr,brpred_inserttaken,brpred_jumpinstr,brpred_addrMismatch);
Line 536... Line 543...
         cycle1prev<=1;
         cycle1prev<=1;
         IP<=fetchaddr+4;
         IP<=fetchaddr+4;
         IP2<=fetchaddr;
         IP2<=fetchaddr;
         multiCycleStall[1]<=multiCycleStall[0];
         multiCycleStall[1]<=multiCycleStall[0];
         multiCycleStall[0]<=0;
         multiCycleStall[0]<=0;
 
          if (irq)
 
            begin
 
              stginhibit<=5'b11110;
 
              codeMiss<=0;
 
              IP<=irq_handler;
 
              irq_bits<=irq;
 
            end
        end
        end
      else  cycle1prev<=0;
      else  cycle1prev<=0;
 
 
      //cycle 2
      //cycle 2
      if (!stall && !stginhibit[1])
      if (!stall && !stginhibit[1])
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              stginhibit<=5'b11110;
              stginhibit<=5'b11110;
              codeMiss<=0;
              codeMiss<=0;
              IP<=IP5;
              IP<=IP5;
              multiCycleStall[0]<=1;
              multiCycleStall[0]<=1;
            end
            end
 
          else if (wrspec)
 
            begin
 
              case (instr4[31:16])
 
                16'd0: irq_handler<=opF;
 
              endcase
 
            end
        end
        end
      else
      else
        begin
        begin
          rAfwd<=0;
          rAfwd<=0;
          rBfwd<=0;
          rBfwd<=0;

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