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module aluplus(instr, val1, val2, valres, wrtval, cjmpinstr,cjmp,const1,retaddr);
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module aluplus(instr, val1, val2, valres, wrtval, cjmpinstr,cjmp,const1,retaddr,wrspec);
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input [31:0] instr, val1, val2;
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input [31:0] instr, val1, val2;
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output [31:0] valres;
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output [31:0] valres;
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output wire wrtval,cjmpinstr;
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output wire wrtval,cjmpinstr;
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output cjmp;
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output cjmp;
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input [31:0] const1;
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input [31:0] const1;
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input [31:0] retaddr;
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input [31:0] retaddr;
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output wrspec;
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wire [5:0] code;
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wire [5:0] code;
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wire [31:0] valcmp;
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wire [31:0] valcmp;
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wire CF,NF,VF,ZF;
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wire CF,NF,VF,ZF;
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/*
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/*
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assign valres=(code==7) ? val1 ^ const1 : 32'bz;
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assign valres=(code==7) ? val1 ^ const1 : 32'bz;
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assign valres=(code==8) ? val1 + val2 : 32'bz;
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assign valres=(code==8) ? val1 + val2 : 32'bz;
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assign valres=(code==9) ? val1 + const1 : 32'bz;
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assign valres=(code==9) ? val1 + const1 : 32'bz;
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assign valres=(code==10)? val1 - val2 : 32'bz;
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assign valres=(code==10)? val1 - val2 : 32'bz;
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assign valres=(code==11)? val1 - const1 : 32'bz;
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assign valres=(code==11)? val1 - const1 : 32'bz;
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//12=no-op
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assign valres=wrspec ? val1 : 32'bz;
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assign valres=(code==13)? val1 & {16'b1111111111111111, const1[15:0]} : 32'bz;
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assign valres=(code==13)? val1 & {16'b1111111111111111, const1[15:0]} : 32'bz;
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assign valres=(code==46) ? retaddr : 32'bz;
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assign valres=(code==46) ? retaddr : 32'bz;
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assign valres=(code==14)? val1 << val2[5:0] : 32'bz;
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assign valres=(code==14)? val1 << val2[5:0] : 32'bz;
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assign valres=(code==15)? val1 << const1[5:0] : 32'bz;
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assign valres=(code==15)? val1 << const1[5:0] : 32'bz;
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assign valres=(code==16)? val1 >> val2[5:0] : 32'bz;
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assign valres=(code==16)? val1 >> val2[5:0] : 32'bz;
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assign valres=(code==17)? val1 >> const1[5:0] : 32'bz;
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assign valres=(code==17)? val1 >> const1[5:0] : 32'bz;
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assign valres=(code==18)? {32{val1[31]},val1} >> val2[5:0] : 32'bz;
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assign valres=(code==18)? {32{val1[31]},val1} >> val2[5:0] : 32'bz;
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assign valres=(code==19)? {32{val1[31]},val1} >> const1[5:0] : 32'bz;
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assign valres=(code==19)? {32{val1[31]},val1} >> const1[5:0] : 32'bz;
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assign valres=wrtval ? 32'bz : 32'b0;
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assign valres=wrtval | wrspec ? 32'bz : 32'b0;
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assign wrtval=((code<=11) || (code>=13 && code<=19) || (code==46));
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assign wrtval=((code<=11) || (code>=13 && code<=19) || (code==46));
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assign wrspec=(code==12) && (instr[15:6]=10'd1);
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//flags for compare &jump
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//flags for compare &jump
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assign {CF,valcmp}=val1 - val2;
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assign {CF,valcmp}=val1 - val2;
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assign NF=valcmp[31];
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assign NF=valcmp[31];
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assign ZF=(val1==val2);
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assign ZF=(val1==val2);
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endmodule
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endmodule
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module cpu(input clk,input busEnRead,input busEnWrite, input busDataReady, output wire busRead, output wire busWrite,output wire [31:0] busAddr,
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module cpu(input clk,input busEnRead,input busEnWrite, input busDataReady, output wire busRead, output wire busWrite,output wire [31:0] busAddr,
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input [511:0] busInput,output wire [511:0] busOutput,
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input [511:0] busInput,output wire [511:0] busOutput,
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output wire [31:0] ioBusAddr,output wire [1:0] ioBusSize, output wire [31:0] ioBusOut, input [31:0] ioBusIn, input ioBusRdy,
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output wire [31:0] ioBusAddr,output wire [1:0] ioBusSize, output wire [31:0] ioBusOut, input [31:0] ioBusIn, input ioBusRdy,
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output wire ioBusWr,output wire ioBusRd,output wire [3:0] dummy);
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output wire ioBusWr,output wire ioBusRd,output wire [3:0] dummy, input [15:0] irq);
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wire [31:0] fetchaddr,fetchdata,readaddr,readdata;
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wire [31:0] fetchaddr,fetchdata,readaddr,readdata;
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reg [31:0] readaddr_reg;
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reg [31:0] readaddr_reg;
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reg [4:0] stginhibit=5'b11110;
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reg [4:0] stginhibit=5'b11110;
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reg [4:0] stginhibit_wrt;
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reg [4:0] stginhibit_wrt;
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reg [31:0] IP=32'b0,IP2,IP3,IP4,IP5,instr=0,instr4=0;
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reg [31:0] IP=32'b0,IP2,IP3,IP4,IP5,instr=0,instr4=0;
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wire wasGlobalStall=multiCycleStall[4];
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wire wasGlobalStall=multiCycleStall[4];
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wire ioInstrWrtVal;
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wire ioInstrWrtVal;
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wire ioInstrDoStall;
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wire ioInstrDoStall;
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wire ioInstrKeepStalling;
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wire ioInstrKeepStalling;
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reg [15:0] irq_bits=16'b0;
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reg [31:0] irq_handler=32'hffff_fff0;
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wire wrspec;
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//dataunit data0(clk,stall,stginhibit,readaddr,readdata,agureadsz,agureaden,aguwriteen,opB);
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//dataunit data0(clk,stall,stginhibit,readaddr,readdata,agureadsz,agureaden,aguwriteen,opB);
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datacache datacache0(clk,stall,stginhibit,codeMiss,dcAddr,dcDataA,busInput,opB,dcHit,dcReadEn,dcWriteEn,dcInsert,dcInitEntry,agureadsz,dcOldAddr);
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datacache datacache0(clk,stall,stginhibit,codeMiss,dcAddr,dcDataA,busInput,opB,dcHit,dcReadEn,dcWriteEn,dcInsert,dcInitEntry,agureadsz,dcOldAddr);
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regfileint0 regf0(clk,intregwe,rA,rB,rC,rF,intregdataA,intregdataB,intregdataC,intregdataF);
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regfileint0 regf0(clk,intregwe,rA,rB,rC,rF,intregdataA,intregdataB,intregdataC,intregdataF);
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aluplus alu0(instr4,opA,opB,opF,aluwrtval,alucjmpinstr,alucjmp,constBits4,retAddr);
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aluplus alu0(instr4,opA,opB,opF,aluwrtval,alucjmpinstr,alucjmp,constBits4,retAddr,wrspec);
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ioinstr ioinstr0(clk,stall,stginhibit,instr4,opA,opB,ioInstrResult,wasGlobalStall,ioInstrWrtVal,ioInstrDoStall,ioInstrKeepStalling,
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ioinstr ioinstr0(clk,stall,stginhibit,instr4,opA,opB,ioInstrResult,wasGlobalStall,ioInstrWrtVal,ioInstrDoStall,ioInstrKeepStalling,
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ioBusAddr,ioBusSize,ioBusOut,ioBusIn,ioBusRdy,ioBusWr,ioBusRd);
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ioBusAddr,ioBusSize,ioBusOut,ioBusIn,ioBusRdy,ioBusWr,ioBusRd);
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subagu agu0(clk,stall,stginhibit,opC,instr0,instr,instr4,aguaddr,aguwrtval,agustall,agureadsz,agureaden,aguwriteen,constBits);
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subagu agu0(clk,stall,stginhibit,opC,instr0,instr,instr4,aguaddr,aguwrtval,agustall,agureadsz,agureaden,aguwriteen,constBits);
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brpred brpred0(clk,stall,stginhibit,fetchaddr,brpred_hit,brpred_instr,brpred_nextaddr,brpred_taken,
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brpred brpred0(clk,stall,stginhibit,fetchaddr,brpred_hit,brpred_instr,brpred_nextaddr,brpred_taken,
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brpred_instertaddr,brpred_instertinstr,brpred_insertnextaddr,brpred_inserttaken,brpred_jumpinstr,brpred_addrMismatch);
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brpred_instertaddr,brpred_instertinstr,brpred_insertnextaddr,brpred_inserttaken,brpred_jumpinstr,brpred_addrMismatch);
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cycle1prev<=1;
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cycle1prev<=1;
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IP<=fetchaddr+4;
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IP<=fetchaddr+4;
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IP2<=fetchaddr;
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IP2<=fetchaddr;
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multiCycleStall[1]<=multiCycleStall[0];
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multiCycleStall[1]<=multiCycleStall[0];
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multiCycleStall[0]<=0;
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multiCycleStall[0]<=0;
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if (irq)
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begin
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stginhibit<=5'b11110;
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codeMiss<=0;
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IP<=irq_handler;
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irq_bits<=irq;
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end
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end
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end
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else cycle1prev<=0;
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else cycle1prev<=0;
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//cycle 2
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//cycle 2
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if (!stall && !stginhibit[1])
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if (!stall && !stginhibit[1])
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Line 664... |
stginhibit<=5'b11110;
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stginhibit<=5'b11110;
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codeMiss<=0;
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codeMiss<=0;
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IP<=IP5;
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IP<=IP5;
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multiCycleStall[0]<=1;
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multiCycleStall[0]<=1;
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end
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end
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else if (wrspec)
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begin
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case (instr4[31:16])
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16'd0: irq_handler<=opF;
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endcase
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end
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end
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end
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else
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else
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begin
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begin
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rAfwd<=0;
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rAfwd<=0;
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rBfwd<=0;
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rBfwd<=0;
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