| Line 23... |
Line 23... |
// ============================================================================
|
// ============================================================================
|
//
|
//
|
`include "FT64_defines.vh"
|
`include "FT64_defines.vh"
|
`include "FT64_config.vh"
|
`include "FT64_config.vh"
|
|
|
module FT64_alu(rst, clk, ld, abort, instr, sz, tlb, store, a, b, c, t, pc, Ra, tgt, tgt2, ven, vm,
|
module FT64_alu(rst, clk, ld, abort, instr, sz, store, a, b, c, t, pc, Ra, tgt, tgt2, ven, vm,
|
csr, o, ob, done, idle, excen, exc, thrd, ptrmask, state, mem, shift,
|
csr, o, ob, done, idle, excen, exc, thrd, ptrmask, state, mem, shift,
|
ol, dl, ASID, icl_i, cyc_i, we_i, vadr_i, cyc_o, we_o, padr_o, uncached, tlb_miss,
|
ol, dl
|
exv_o, rdv_o, wrv_o
|
|
`ifdef SUPPORT_BBMS
|
`ifdef SUPPORT_BBMS
|
, pb, cbl, cbu, ro, dbl, dbu, sbl, sbu, en
|
, pb, cbl, cbu, ro, dbl, dbu, sbl, sbu, en
|
`endif
|
`endif
|
);
|
);
|
parameter DBW = 64;
|
parameter DBW = 64;
|
| Line 45... |
Line 44... |
input clk;
|
input clk;
|
input ld;
|
input ld;
|
input abort;
|
input abort;
|
input [47:0] instr;
|
input [47:0] instr;
|
input [2:0] sz;
|
input [2:0] sz;
|
input tlb;
|
|
input store;
|
input store;
|
input [63:0] a;
|
input [63:0] a;
|
input [63:0] b;
|
input [63:0] b;
|
input [63:0] c;
|
input [63:0] c;
|
input [63:0] t; // target register value
|
input [63:0] t; // target register value
|
| Line 71... |
Line 69... |
input [1:0] state;
|
input [1:0] state;
|
input mem;
|
input mem;
|
input shift;
|
input shift;
|
input [1:0] ol;
|
input [1:0] ol;
|
input [1:0] dl;
|
input [1:0] dl;
|
input [7:0] ASID;
|
|
input icl_i;
|
|
input cyc_i;
|
|
input we_i;
|
|
input [ABW-1:0] vadr_i;
|
|
output cyc_o;
|
|
output we_o;
|
|
output [ABW-1:0] padr_o;
|
|
output uncached;
|
|
output tlb_miss;
|
|
output wrv_o;
|
|
output rdv_o;
|
|
output exv_o;
|
|
`ifdef SUPPORT_BBMS
|
`ifdef SUPPORT_BBMS
|
input [63:0] pb;
|
input [63:0] pb;
|
input [63:0] cbl;
|
input [63:0] cbl;
|
input [63:0] cbu;
|
input [63:0] cbu;
|
input [63:0] ro;
|
input [63:0] ro;
|
| Line 280... |
Line 265... |
6'h20: shift10 <= ~shift9; // COM
|
6'h20: shift10 <= ~shift9; // COM
|
6'h21: shift10 <= !shift9; // NOT
|
6'h21: shift10 <= !shift9; // NOT
|
default: shift10 <= shift9;
|
default: shift10 <= shift9;
|
endcase
|
endcase
|
|
|
wire tlb_done, tlb_idle;
|
|
wire [DBW-1:0] tlbo;
|
|
|
|
`ifdef SUPPORT_TLB
|
|
FT64_TLB utlb1 (
|
|
.rst(rst),
|
|
.clk(clk),
|
|
.ld(ld & tlb),
|
|
.done(tlb_done),
|
|
.idle(tlb_idle),
|
|
.ol(ol),
|
|
.ASID(ASID),
|
|
.op(instr[25:22]),
|
|
.regno(instr[21:18]),
|
|
.dati(a),
|
|
.dato(tlbo),
|
|
.uncached(uncached),
|
|
.icl_i(icl_i),
|
|
.cyc_i(cyc_i),
|
|
.we_i(we_i),
|
|
.vadr_i(vadr_i),
|
|
.cyc_o(cyc_o),
|
|
.we_o(we_o),
|
|
.padr_o(padr_o),
|
|
.TLBMiss(tlb_miss),
|
|
.wrv_o(wrv_o),
|
|
.rdv_o(rdv_o),
|
|
.exv_o(exv_o),
|
|
.HTLBVirtPageo()
|
|
);
|
|
`else
|
|
assign tlbo = 64'hDEADDEADDEADDEAD;
|
|
assign uncached = 1'b0;
|
|
assign padr_o = vadr_i;
|
|
assign cyc_o = cyc_i;
|
|
assign we_o = we_i;
|
|
assign tlb_miss = 1'b0;
|
|
assign wrv_o = 1'b0;
|
|
assign rdv_o = 1'b0;
|
|
assign exv_o = 1'b0;
|
|
`endif
|
|
|
|
FT64_bitfield #(DBW) ubf1
|
FT64_bitfield #(DBW) ubf1
|
(
|
(
|
.inst(instr),
|
.inst(instr),
|
.a(a),
|
.a(a),
|
.b(b),
|
.b(b),
|
| Line 1045... |
Line 988... |
$stop;
|
$stop;
|
end
|
end
|
`ADD:
|
`ADD:
|
`ifdef SIMD
|
`ifdef SIMD
|
case(sz)
|
case(sz)
|
3'd0,3'd4:
|
3'd0:
|
|
begin
|
|
o[7:0] = a[7:0] + b[7:0];
|
|
o[63:8] = {56{o[7]}};
|
|
end
|
|
3'd1:
|
|
begin
|
|
o[15:0] = a[15:0] + b[15:0];
|
|
o[63:16] = {48{o[15]}};
|
|
end
|
|
3'd2:
|
|
begin
|
|
o[31:0] = a[31:0] + b[31:0];
|
|
o[63:32] = {32{o[31]}};
|
|
end
|
|
3'd4:
|
begin
|
begin
|
o[7:0] = a[7:0] + b[7:0];
|
o[7:0] = a[7:0] + b[7:0];
|
o[15:8] = a[15:8] + b[15:8];
|
o[15:8] = a[15:8] + b[15:8];
|
o[23:16] = a[23:16] + b[23:16];
|
o[23:16] = a[23:16] + b[23:16];
|
o[31:24] = a[31:24] + b[31:24];
|
o[31:24] = a[31:24] + b[31:24];
|
o[39:32] = a[39:32] + b[39:32];
|
o[39:32] = a[39:32] + b[39:32];
|
o[47:40] = a[47:40] + b[47:40];
|
o[47:40] = a[47:40] + b[47:40];
|
o[55:48] = a[55:48] + b[55:48];
|
o[55:48] = a[55:48] + b[55:48];
|
o[63:56] = a[63:56] + b[63:56];
|
o[63:56] = a[63:56] + b[63:56];
|
end
|
end
|
3'd1,3'd5:
|
3'd5:
|
begin
|
begin
|
o[15:0] = a[15:0] + b[15:0];
|
o[15:0] = a[15:0] + b[15:0];
|
o[31:16] = a[31:16] + b[31:16];
|
o[31:16] = a[31:16] + b[31:16];
|
o[47:32] = a[47:32] + b[47:32];
|
o[47:32] = a[47:32] + b[47:32];
|
o[63:48] = a[63:48] + b[63:48];
|
o[63:48] = a[63:48] + b[63:48];
|
end
|
end
|
3'd2,3'd6:
|
3'd6:
|
begin
|
begin
|
o[31:0] = a[31:0] + b[31:0];
|
o[31:0] = a[31:0] + b[31:0];
|
o[63:32] = a[63:32] + b[63:32];
|
o[63:32] = a[63:32] + b[63:32];
|
end
|
end
|
default:
|
default:
|
| Line 1076... |
Line 1034... |
end
|
end
|
endcase
|
endcase
|
`else
|
`else
|
o = a + b;
|
o = a + b;
|
`endif
|
`endif
|
// If the operation is SIMD the target register must be passed in arg T.
|
|
`SUB:
|
`SUB:
|
`ifdef SIMD
|
`ifdef SIMD
|
case(sz)
|
case(sz)
|
3'd0:
|
3'd0:
|
begin
|
begin
|
o[7:0] = a[7:0] - b[7:0];
|
o[7:0] = a[7:0] - b[7:0];
|
o[63:8] = t[63:8];
|
o[63:8] = {56{o[7]}};
|
|
end
|
|
3'd1:
|
|
begin
|
|
o[15:0] = a[15:0] - b[15:0];
|
|
o[63:16] = {48{o[15]}};
|
|
end
|
|
3'd2:
|
|
begin
|
|
o[31:0] = a[31:0] - b[31:0];
|
|
o[63:32] = {31{o[31]}};
|
end
|
end
|
3'd4:
|
3'd4:
|
begin
|
begin
|
o[7:0] = a[7:0] - b[7:0];
|
o[7:0] = a[7:0] - b[7:0];
|
o[15:8] = a[15:8] - b[15:8];
|
o[15:8] = a[15:8] - b[15:8];
|
| Line 1096... |
Line 1063... |
o[39:32] = a[39:32] - b[39:32];
|
o[39:32] = a[39:32] - b[39:32];
|
o[47:40] = a[47:40] - b[47:40];
|
o[47:40] = a[47:40] - b[47:40];
|
o[55:48] = a[55:48] - b[55:48];
|
o[55:48] = a[55:48] - b[55:48];
|
o[63:56] = a[63:56] - b[63:56];
|
o[63:56] = a[63:56] - b[63:56];
|
end
|
end
|
3'd1,3'd5:
|
3'd5:
|
begin
|
begin
|
o[15:0] = a[15:0] - b[15:0];
|
o[15:0] = a[15:0] - b[15:0];
|
o[31:16] = a[31:16] - b[31:16];
|
o[31:16] = a[31:16] - b[31:16];
|
o[47:32] = a[47:32] - b[47:32];
|
o[47:32] = a[47:32] - b[47:32];
|
o[63:48] = a[63:48] - b[63:48];
|
o[63:48] = a[63:48] - b[63:48];
|
end
|
end
|
3'd2,3'd6:
|
3'd6:
|
begin
|
begin
|
o[31:0] = a[31:0] - b[31:0];
|
o[31:0] = a[31:0] - b[31:0];
|
o[63:32] = a[63:32] - b[63:32];
|
o[63:32] = a[63:32] - b[63:32];
|
end
|
end
|
default:
|
default:
|
begin
|
begin
|
o[63:0] = a - b;
|
o = a - b;
|
end
|
end
|
endcase
|
endcase
|
`else
|
`else
|
o = a - b;
|
o = a - b;
|
`endif
|
`endif
|
| Line 1158... |
Line 1125... |
//o[63:44] = PTR;
|
//o[63:44] = PTR;
|
end
|
end
|
`MIN:
|
`MIN:
|
`ifdef SIMD
|
`ifdef SIMD
|
case(sz)
|
case(sz)
|
3'd0:
|
3'd0: o = BIG ? ($signed(a[7:0]) < $signed(b[7:0]) ? {{56{a[7]}},a[7:0]} : {{56{b[7]}},b[7:0]}) : 64'hCCCCCCCCCCCCCCCC;
|
begin
|
3'd1: o = BIG ? ($signed(a[15:0]) < $signed(b[15:0]) ? {{48{a[15]}},a[15:0]} : {{48{b[15]}},b[15:0]}) : 64'hCCCCCCCCCCCCCCCC;
|
o[7:0] = BIG ? ($signed(a[7:0]) < $signed(b[7:0]) ? a[7:0] : b[7:0]) : 8'hCC;
|
3'd2: o = BIG ? ($signed(a[31:0]) < $signed(b[31:0]) ? {{32{a[31]}},a[31:0]} : {{32{b[31]}},b[31:0]}) : 64'hCCCCCCCCCCCCCCCC;
|
o[63:8] = BIG ? t[63:8] : 56'hCCCCCCCCCCCCCC;
|
3'd3: o = BIG ? ($signed(a) < $signed(b) ? a : b) : 64'hCCCCCCCCCCCCCCCC;
|
end
|
|
3'd1:
|
|
begin
|
|
o[15:0] = BIG ? ($signed(a[15:0]) < $signed(b[15:0]) ? a[15:0] : b[15:0]) : 16'hCCCC;
|
|
o[63:16] = BIG ? t[63:16] : 48'hCCCCCCCCCCCC;
|
|
end
|
|
3'd2:
|
|
begin
|
|
o[31:0] = BIG ? ($signed(a[31:0]) < $signed(b[31:0]) ? a[31:0] : b[31:0]) : 32'hCCCCCCCC;
|
|
o[63:32] = BIG ? t[63:32] : 32'hCCCCCCCC;
|
|
end
|
|
3'd3:
|
|
begin
|
|
o = BIG ? ($signed(a) < $signed(b) ? a : b) : 64'hCCCCCCCCCCCCCCCC;
|
|
end
|
|
3'd4:
|
3'd4:
|
begin
|
begin
|
o[7:0] = BIG ? ($signed(a[7:0]) < $signed(b[7:0]) ? a[7:0] : b[7:0]) : 8'hCC;
|
o[7:0] = BIG ? ($signed(a[7:0]) < $signed(b[7:0]) ? a[7:0] : b[7:0]) : 8'hCC;
|
o[15:8] = BIG ? ($signed(a[15:8]) < $signed(b[15:8]) ? a[15:8] : b[15:8]) : 64'hCCCCCCCCCCCCCCCC;
|
o[15:8] = BIG ? ($signed(a[15:8]) < $signed(b[15:8]) ? a[15:8] : b[15:8]) : 64'hCCCCCCCCCCCCCCCC;
|
o[23:16] = BIG ? ($signed(a[23:16]) < $signed(b[23:16]) ? a[23:16] : b[23:16]) : 64'hCCCCCCCCCCCCCCCC;
|
o[23:16] = BIG ? ($signed(a[23:16]) < $signed(b[23:16]) ? a[23:16] : b[23:16]) : 64'hCCCCCCCCCCCCCCCC;
|
| Line 1211... |
Line 1163... |
o = BIG ? ($signed(a) < $signed(b) ? a : b) : 64'hCCCCCCCCCCCCCCCC;
|
o = BIG ? ($signed(a) < $signed(b) ? a : b) : 64'hCCCCCCCCCCCCCCCC;
|
`endif
|
`endif
|
`MAX:
|
`MAX:
|
`ifdef SIMD
|
`ifdef SIMD
|
case(sz)
|
case(sz)
|
3'd0,3'd4:
|
3'd0: o = BIG ? ($signed(a[7:0]) > $signed(b[7:0]) ? {{56{a[7]}},a[7:0]} : {{56{b[7]}},b[7:0]}) : 64'hCCCCCCCCCCCCCCCC;
|
|
3'd1: o = BIG ? ($signed(a[15:0]) > $signed(b[15:0]) ? {{48{a[15]}},a[15:0]} : {{48{b[15]}},b[15:0]}) : 64'hCCCCCCCCCCCCCCCC;
|
|
3'd2: o = BIG ? ($signed(a[31:0]) > $signed(b[31:0]) ? {{32{a[31]}},a[31:0]} : {{32{b[31]}},b[31:0]}) : 64'hCCCCCCCCCCCCCCCC;
|
|
3'd3: o = BIG ? ($signed(a) > $signed(b) ? a : b) : 64'hCCCCCCCCCCCCCCCC;
|
|
3'd4:
|
begin
|
begin
|
o[7:0] = BIG ? ($signed(a[7:0]) > $signed(b[7:0]) ? a[7:0] : b[7:0]) : 64'hCCCCCCCCCCCCCCCC;
|
o[7:0] = BIG ? ($signed(a[7:0]) > $signed(b[7:0]) ? a[7:0] : b[7:0]) : 64'hCCCCCCCCCCCCCCCC;
|
o[15:8] = BIG ? ($signed(a[15:8]) > $signed(b[15:8]) ? a[15:8] : b[15:8]) : 64'hCCCCCCCCCCCCCCCC;
|
o[15:8] = BIG ? ($signed(a[15:8]) > $signed(b[15:8]) ? a[15:8] : b[15:8]) : 64'hCCCCCCCCCCCCCCCC;
|
o[23:16] = BIG ? ($signed(a[23:16]) > $signed(b[23:16]) ? a[23:16] : b[23:16]) : 64'hCCCCCCCCCCCCCCCC;
|
o[23:16] = BIG ? ($signed(a[23:16]) > $signed(b[23:16]) ? a[23:16] : b[23:16]) : 64'hCCCCCCCCCCCCCCCC;
|
o[31:24] = BIG ? ($signed(a[31:24]) > $signed(b[31:24]) ? a[31:24] : b[31:24]) : 64'hCCCCCCCCCCCCCCCC;
|
o[31:24] = BIG ? ($signed(a[31:24]) > $signed(b[31:24]) ? a[31:24] : b[31:24]) : 64'hCCCCCCCCCCCCCCCC;
|
o[39:32] = BIG ? ($signed(a[39:32]) > $signed(b[39:32]) ? a[39:32] : b[39:32]) : 64'hCCCCCCCCCCCCCCCC;
|
o[39:32] = BIG ? ($signed(a[39:32]) > $signed(b[39:32]) ? a[39:32] : b[39:32]) : 64'hCCCCCCCCCCCCCCCC;
|
o[47:40] = BIG ? ($signed(a[47:40]) > $signed(b[47:40]) ? a[47:40] : b[47:40]) : 64'hCCCCCCCCCCCCCCCC;
|
o[47:40] = BIG ? ($signed(a[47:40]) > $signed(b[47:40]) ? a[47:40] : b[47:40]) : 64'hCCCCCCCCCCCCCCCC;
|
o[55:48] = BIG ? ($signed(a[55:48]) > $signed(b[55:48]) ? a[55:48] : b[55:48]) : 64'hCCCCCCCCCCCCCCCC;
|
o[55:48] = BIG ? ($signed(a[55:48]) > $signed(b[55:48]) ? a[55:48] : b[55:48]) : 64'hCCCCCCCCCCCCCCCC;
|
o[63:56] = BIG ? ($signed(a[63:56]) > $signed(b[63:56]) ? a[63:56] : b[63:56]) : 64'hCCCCCCCCCCCCCCCC;
|
o[63:56] = BIG ? ($signed(a[63:56]) > $signed(b[63:56]) ? a[63:56] : b[63:56]) : 64'hCCCCCCCCCCCCCCCC;
|
end
|
end
|
3'd1,3'd5:
|
3'd5:
|
begin
|
begin
|
o[15:0] = BIG ? ($signed(a[15:0]) > $signed(b[15:0]) ? a[15:0] : b[15:0]) : 64'hCCCCCCCCCCCCCCCC;
|
o[15:0] = BIG ? ($signed(a[15:0]) > $signed(b[15:0]) ? a[15:0] : b[15:0]) : 64'hCCCCCCCCCCCCCCCC;
|
o[32:16] = BIG ? ($signed(a[32:16]) > $signed(b[32:16]) ? a[32:16] : b[32:16]) : 64'hCCCCCCCCCCCCCCCC;
|
o[32:16] = BIG ? ($signed(a[32:16]) > $signed(b[32:16]) ? a[32:16] : b[32:16]) : 64'hCCCCCCCCCCCCCCCC;
|
o[47:32] = BIG ? ($signed(a[47:32]) > $signed(b[47:32]) ? a[47:32] : b[47:32]) : 64'hCCCCCCCCCCCCCCCC;
|
o[47:32] = BIG ? ($signed(a[47:32]) > $signed(b[47:32]) ? a[47:32] : b[47:32]) : 64'hCCCCCCCCCCCCCCCC;
|
o[63:48] = BIG ? ($signed(a[63:48]) > $signed(b[63:48]) ? a[63:48] : b[63:48]) : 64'hCCCCCCCCCCCCCCCC;
|
o[63:48] = BIG ? ($signed(a[63:48]) > $signed(b[63:48]) ? a[63:48] : b[63:48]) : 64'hCCCCCCCCCCCCCCCC;
|
end
|
end
|
3'd2,3'd6:
|
3'd6:
|
begin
|
begin
|
o[31:0] = BIG ? ($signed(a[31:0]) > $signed(b[31:0]) ? a[31:0] : b[31:0]) : 64'hCCCCCCCCCCCCCCCC;
|
o[31:0] = BIG ? ($signed(a[31:0]) > $signed(b[31:0]) ? a[31:0] : b[31:0]) : 64'hCCCCCCCCCCCCCCCC;
|
o[63:32] = BIG ? ($signed(a[63:32]) > $signed(b[63:32]) ? a[63:32] : b[63:32]) : 64'hCCCCCCCCCCCCCCCC;
|
o[63:32] = BIG ? ($signed(a[63:32]) > $signed(b[63:32]) ? a[63:32] : b[63:32]) : 64'hCCCCCCCCCCCCCCCC;
|
end
|
end
|
3'd3,3'd7:
|
3'd7:
|
begin
|
begin
|
o[63:0] = BIG ? ($signed(a) > $signed(b) ? a : b) : 64'hCCCCCCCCCCCCCCCC;
|
o[63:0] = BIG ? ($signed(a) > $signed(b) ? a : b) : 64'hCCCCCCCCCCCCCCCC;
|
end
|
end
|
endcase
|
endcase
|
`else
|
`else
|
| Line 1262... |
Line 1218... |
`RTSGT: o = as > bs;
|
`RTSGT: o = as > bs;
|
`RTSEQ: o = as==bs;
|
`RTSEQ: o = as==bs;
|
`RTSNE: o = as!=bs;
|
`RTSNE: o = as!=bs;
|
endcase
|
endcase
|
*/
|
*/
|
`TLB: o = BIG ? tlbo : 64'hDEADDEADDEADDEAD;
|
|
default: o[63:0] = 64'hDEADDEADDEADDEAD;
|
default: o[63:0] = 64'hDEADDEADDEADDEAD;
|
endcase
|
endcase
|
`MEMNDX:
|
`MEMNDX:
|
if (instr[7:6]==2'b10) begin
|
if (instr[7:6]==2'b10) begin
|
if (instr[31])
|
if (instr[31])
|
| Line 1508... |
Line 1463... |
done <= div_done;
|
done <= div_done;
|
else if (IsShiftAndOp(instr) & BIG)
|
else if (IsShiftAndOp(instr) & BIG)
|
done <= sao_done;
|
done <= sao_done;
|
else if (shift)
|
else if (shift)
|
done <= adrDone;
|
done <= adrDone;
|
else if (tlb & BIG)
|
|
done <= tlb_done;
|
|
else
|
else
|
done <= TRUE;
|
done <= TRUE;
|
end
|
end
|
|
|
// Generate idle signal
|
// Generate idle signal
|
| Line 1533... |
Line 1486... |
idle <= div_idle;
|
idle <= div_idle;
|
else if (IsShiftAndOp(instr) & BIG)
|
else if (IsShiftAndOp(instr) & BIG)
|
idle <= sao_idle;
|
idle <= sao_idle;
|
else if (shift)
|
else if (shift)
|
idle <= adrIdle;
|
idle <= adrIdle;
|
else if (tlb & BIG)
|
|
idle <= tlb_idle;
|
|
else
|
else
|
idle <= TRUE;
|
idle <= TRUE;
|
end
|
end
|
|
|
function fnOverflow;
|
function fnOverflow;
|
| Line 1663... |
Line 1614... |
else if (usa < {ro[50:0],13'd0} && store && dl!=2'b00)
|
else if (usa < {ro[50:0],13'd0} && store && dl!=2'b00)
|
exc <= `FLT_WRV;
|
exc <= `FLT_WRV;
|
else
|
else
|
`endif
|
`endif
|
casez(b[2:0])
|
casez(b[2:0])
|
3'b100: exc <= o[2:0]!=3'b0 ? `FLT_NONE : `FLT_NONE; // LW / SW
|
3'b100: exc <= (o[2:0]!=3'b0) ? `FLT_NONE : `FLT_NONE; // LW / SW
|
3'b?10: exc <= o[1:0]!=2'b0 ? `FLT_ALN : `FLT_NONE; // LH / LHU / SH
|
3'b?10: exc <= (o[1:0]!=2'b0) ? `FLT_NONE : `FLT_NONE; // LH / LHU / SH
|
default: exc <= o[ 0] ? `FLT_ALN : `FLT_NONE; // LC / LCU / SC
|
default: exc <= o[ 0] ? `FLT_NONE : `FLT_NONE; // LC / LCU / SC
|
endcase
|
endcase
|
end
|
end
|
`LWR,`SWC,`CAS,`CACHE:
|
`LWR,`SWC,`CAS,`CACHE:
|
begin
|
begin
|
`ifdef SUPPORT_BBMS
|
`ifdef SUPPORT_BBMS
|
| Line 1711... |
Line 1662... |
3'd0: o[63:0] = $signed(a[7:0]) == $signed(b[7:0]);
|
3'd0: o[63:0] = $signed(a[7:0]) == $signed(b[7:0]);
|
3'd1: o[63:0] = $signed(a[15:0]) == $signed(b[15:0]);
|
3'd1: o[63:0] = $signed(a[15:0]) == $signed(b[15:0]);
|
3'd2: o[63:0] = $signed(a[31:0]) == $signed(b[31:0]);
|
3'd2: o[63:0] = $signed(a[31:0]) == $signed(b[31:0]);
|
3'd3: o[63:0] = $signed(a) == $signed(b);
|
3'd3: o[63:0] = $signed(a) == $signed(b);
|
3'd4: o[63:0] = {
|
3'd4: o[63:0] = {
|
7'h0,$signed(a[7:0]) == $signed(b[7:0]),
|
7'h0,$signed(a[63:56]) == $signed(b[63:56]),
|
7'h0,$signed(a[15:8]) == $signed(b[15:8]),
|
|
7'h0,$signed(a[23:16]) == $signed(b[23:16]),
|
|
7'h0,$signed(a[31:24]) == $signed(b[31:24]),
|
|
7'h0,$signed(a[39:32]) == $signed(b[39:32]),
|
|
7'h0,$signed(a[47:40]) == $signed(b[47:40]),
|
|
7'h0,$signed(a[55:48]) == $signed(b[55:48]),
|
7'h0,$signed(a[55:48]) == $signed(b[55:48]),
|
7'h0,$signed(a[63:56]) == $signed(b[63:56])
|
7'h0,$signed(a[47:40]) == $signed(b[47:40]),
|
|
7'h0,$signed(a[39:32]) == $signed(b[39:32]),
|
|
7'h0,$signed(a[31:24]) == $signed(b[31:24]),
|
|
7'h0,$signed(a[23:16]) == $signed(b[23:16]),
|
|
7'h0,$signed(a[15:8]) == $signed(b[15:8]),
|
|
7'h0,$signed(a[7:0]) == $signed(b[7:0])
|
};
|
};
|
3'd5: o[63:0] = {
|
3'd5: o[63:0] = {
|
15'h0,$signed(a[15:0]) == $signed(b[15:0]),
|
15'h0,$signed(a[63:48]) == $signed(b[63:48]),
|
15'h0,$signed(a[31:16]) == $signed(b[31:16]),
|
|
15'h0,$signed(a[47:32]) == $signed(b[47:32]),
|
15'h0,$signed(a[47:32]) == $signed(b[47:32]),
|
15'h0,$signed(a[63:48]) == $signed(b[63:48])
|
15'h0,$signed(a[31:16]) == $signed(b[31:16]),
|
|
15'h0,$signed(a[15:0]) == $signed(b[15:0])
|
};
|
};
|
3'd6: o[63:0] = {
|
3'd6: o[63:0] = {
|
31'h0,$signed(a[31:0]) == $signed(b[31:0]),
|
31'h0,$signed(a[63:32]) == $signed(b[63:32]),
|
31'h0,$signed(a[63:32]) == $signed(b[63:32])
|
31'h0,$signed(a[31:0]) == $signed(b[31:0])
|
};
|
};
|
3'd7: o[63:0] = $signed(a[63:0]) == $signed(b[63:0]);
|
3'd7: o[63:0] = $signed(a[63:0]) == $signed(b[63:0]);
|
endcase
|
endcase
|
`else
|
`else
|
o = $signed(a) == $signed(b);
|
o = $signed(a) == $signed(b);
|
| Line 1752... |
Line 1703... |
3'd0: o[63:0] = $signed(a[7:0]) < $signed(b[7:0]);
|
3'd0: o[63:0] = $signed(a[7:0]) < $signed(b[7:0]);
|
3'd1: o[63:0] = $signed(a[15:0]) < $signed(b[15:0]);
|
3'd1: o[63:0] = $signed(a[15:0]) < $signed(b[15:0]);
|
3'd2: o[63:0] = $signed(a[31:0]) < $signed(b[31:0]);
|
3'd2: o[63:0] = $signed(a[31:0]) < $signed(b[31:0]);
|
3'd3: o[63:0] = $signed(a) < $signed(b);
|
3'd3: o[63:0] = $signed(a) < $signed(b);
|
3'd4: o[63:0] = {
|
3'd4: o[63:0] = {
|
7'h0,$signed(a[7:0]) < $signed(b[7:0]),
|
7'h0,$signed(a[63:56]) < $signed(b[63:56]),
|
7'h0,$signed(a[15:8]) < $signed(b[15:8]),
|
|
7'h0,$signed(a[23:16]) < $signed(b[23:16]),
|
|
7'h0,$signed(a[31:24]) < $signed(b[31:24]),
|
|
7'h0,$signed(a[39:32]) < $signed(b[39:32]),
|
|
7'h0,$signed(a[47:40]) < $signed(b[47:40]),
|
|
7'h0,$signed(a[55:48]) < $signed(b[55:48]),
|
7'h0,$signed(a[55:48]) < $signed(b[55:48]),
|
7'h0,$signed(a[63:56]) < $signed(b[63:56])
|
7'h0,$signed(a[47:40]) < $signed(b[47:40]),
|
|
7'h0,$signed(a[39:32]) < $signed(b[39:32]),
|
|
7'h0,$signed(a[31:24]) < $signed(b[31:24]),
|
|
7'h0,$signed(a[23:16]) < $signed(b[23:16]),
|
|
7'h0,$signed(a[15:8]) < $signed(b[15:8]),
|
|
7'h0,$signed(a[7:0]) < $signed(b[7:0])
|
};
|
};
|
3'd5: o[63:0] = {
|
3'd5: o[63:0] = {
|
15'h0,$signed(a[15:0]) < $signed(b[15:0]),
|
15'h0,$signed(a[63:48]) < $signed(b[63:48]),
|
15'h0,$signed(a[31:16]) < $signed(b[31:16]),
|
|
15'h0,$signed(a[47:32]) < $signed(b[47:32]),
|
15'h0,$signed(a[47:32]) < $signed(b[47:32]),
|
15'h0,$signed(a[63:48]) < $signed(b[63:48])
|
15'h0,$signed(a[31:16]) < $signed(b[31:16]),
|
|
15'h0,$signed(a[15:0]) < $signed(b[15:0])
|
};
|
};
|
3'd6: o[63:0] = {
|
3'd6: o[63:0] = {
|
31'h0,$signed(a[31:0]) < $signed(b[31:0]),
|
31'h0,$signed(a[63:32]) < $signed(b[63:32]),
|
31'h0,$signed(a[63:32]) < $signed(b[63:32])
|
31'h0,$signed(a[31:0]) < $signed(b[31:0])
|
};
|
};
|
3'd7: o[63:0] = $signed(a[63:0]) < $signed(b[63:0]);
|
3'd7: o[63:0] = $signed(a[63:0]) < $signed(b[63:0]);
|
endcase
|
endcase
|
`else
|
`else
|
o[63:0] = $signed(a[63:0]) < $signed(b[63:0]);
|
o[63:0] = $signed(a[63:0]) < $signed(b[63:0]);
|
| Line 1793... |
Line 1744... |
3'd0: o[63:0] = $signed(a[7:0]) <= $signed(b[7:0]);
|
3'd0: o[63:0] = $signed(a[7:0]) <= $signed(b[7:0]);
|
3'd1: o[63:0] = $signed(a[15:0]) <= $signed(b[15:0]);
|
3'd1: o[63:0] = $signed(a[15:0]) <= $signed(b[15:0]);
|
3'd2: o[63:0] = $signed(a[31:0]) <= $signed(b[31:0]);
|
3'd2: o[63:0] = $signed(a[31:0]) <= $signed(b[31:0]);
|
3'd3: o[63:0] = $signed(a) <= $signed(b);
|
3'd3: o[63:0] = $signed(a) <= $signed(b);
|
3'd4: o[63:0] = {
|
3'd4: o[63:0] = {
|
7'h0,$signed(a[7:0]) <= $signed(b[7:0]),
|
7'h0,$signed(a[63:56]) <= $signed(b[63:56]),
|
7'h0,$signed(a[15:8]) <= $signed(b[15:8]),
|
|
7'h0,$signed(a[23:16]) <= $signed(b[23:16]),
|
|
7'h0,$signed(a[31:24]) <= $signed(b[31:24]),
|
|
7'h0,$signed(a[39:32]) <= $signed(b[39:32]),
|
|
7'h0,$signed(a[47:40]) <= $signed(b[47:40]),
|
|
7'h0,$signed(a[55:48]) <= $signed(b[55:48]),
|
7'h0,$signed(a[55:48]) <= $signed(b[55:48]),
|
7'h0,$signed(a[63:56]) <= $signed(b[63:56])
|
7'h0,$signed(a[47:40]) <= $signed(b[47:40]),
|
|
7'h0,$signed(a[39:32]) <= $signed(b[39:32]),
|
|
7'h0,$signed(a[31:24]) <= $signed(b[31:24]),
|
|
7'h0,$signed(a[23:16]) <= $signed(b[23:16]),
|
|
7'h0,$signed(a[15:8]) <= $signed(b[15:8]),
|
|
7'h0,$signed(a[7:0]) <= $signed(b[7:0])
|
};
|
};
|
3'd5: o[63:0] = {
|
3'd5: o[63:0] = {
|
15'h0,$signed(a[15:0]) <= $signed(b[15:0]),
|
15'h0,$signed(a[63:48]) <= $signed(b[63:48]),
|
15'h0,$signed(a[31:16]) <= $signed(b[31:16]),
|
|
15'h0,$signed(a[47:32]) <= $signed(b[47:32]),
|
15'h0,$signed(a[47:32]) <= $signed(b[47:32]),
|
15'h0,$signed(a[63:48]) <= $signed(b[63:48])
|
15'h0,$signed(a[31:16]) <= $signed(b[31:16]),
|
|
15'h0,$signed(a[15:0]) <= $signed(b[15:0])
|
};
|
};
|
3'd6: o[63:0] = {
|
3'd6: o[63:0] = {
|
31'h0,$signed(a[31:0]) <= $signed(b[31:0]),
|
31'h0,$signed(a[63:32]) <= $signed(b[63:32]),
|
31'h0,$signed(a[63:32]) <= $signed(b[63:32])
|
31'h0,$signed(a[31:0]) <= $signed(b[31:0])
|
};
|
};
|
3'd7: o[63:0] = $signed(a[63:0]) <= $signed(b[63:0]);
|
3'd7: o[63:0] = $signed(a[63:0]) <= $signed(b[63:0]);
|
endcase
|
endcase
|
`else
|
`else
|
o = $signed(a) <= $signed(b);
|
o = $signed(a) <= $signed(b);
|
| Line 1829... |
Line 1780... |
input [63:0] b;
|
input [63:0] b;
|
output [63:0] o;
|
output [63:0] o;
|
begin
|
begin
|
`ifdef SIMD
|
`ifdef SIMD
|
case(sz[2:0])
|
case(sz[2:0])
|
3'd4,3'd0: o = {
|
3'd0: o = (a[7:0]) < (b[7:0]);
|
7'h0,(a[7:0]) < (b[7:0]),
|
3'd1: o = (a[15:0]) < (b[15:0]);
|
7'h0,(a[15:8]) < (b[15:8]),
|
3'd2: o = (a[31:0]) < (b[31:0]);
|
7'h0,(a[23:16]) < (b[23:16]),
|
3'd4: o = {
|
7'h0,(a[31:24]) < (b[31:24]),
|
7'h0,(a[63:56]) < (b[63:56]),
|
7'h0,(a[39:32]) < (b[39:32]),
|
|
7'h0,(a[47:40]) < (b[47:40]),
|
|
7'h0,(a[55:48]) < (b[55:48]),
|
7'h0,(a[55:48]) < (b[55:48]),
|
7'h0,(a[63:56]) < (b[63:56])
|
7'h0,(a[47:40]) < (b[47:40]),
|
|
7'h0,(a[39:32]) < (b[39:32]),
|
|
7'h0,(a[31:24]) < (b[31:24]),
|
|
7'h0,(a[23:16]) < (b[23:16]),
|
|
7'h0,(a[15:8]) < (b[15:8]),
|
|
7'h0,(a[7:0]) < (b[7:0])
|
};
|
};
|
3'd5,3'd1: o = {
|
3'd5: o = {
|
15'h0,(a[15:0]) < (b[15:0]),
|
15'h0,(a[63:48]) < (b[63:48]),
|
15'h0,(a[31:16]) < (b[31:16]),
|
|
15'h0,(a[47:32]) < (b[47:32]),
|
15'h0,(a[47:32]) < (b[47:32]),
|
15'h0,(a[63:48]) < (b[63:48])
|
15'h0,(a[31:16]) < (b[31:16]),
|
|
15'h0,(a[15:0]) < (b[15:0])
|
};
|
};
|
3'd6,3'd2: o = {
|
3'd6: o = {
|
31'h0,(a[31:0]) < (b[31:0]),
|
31'h0,(a[63:32]) < (b[63:32]),
|
31'h0,(a[63:32]) < (b[63:32])
|
31'h0,(a[31:0]) < (b[31:0])
|
};
|
};
|
3'd7,3'd3: o = (a[63:0]) < (b[63:0]);
|
3'd7,3'd3: o = (a[63:0]) < (b[63:0]);
|
endcase
|
endcase
|
`else
|
`else
|
o = (a) < (b);
|
o = (a) < (b);
|
| Line 1866... |
Line 1820... |
input [63:0] b;
|
input [63:0] b;
|
output [63:0] o;
|
output [63:0] o;
|
begin
|
begin
|
`ifdef SIMD
|
`ifdef SIMD
|
case(sz[2:0])
|
case(sz[2:0])
|
3'd0: o[63:0] = (a[7:0]) <= (b[7:0]);
|
3'd0: o = (a[7:0]) <= (b[7:0]);
|
3'd1: o[63:0] = (a[15:0]) <= (b[15:0]);
|
3'd1: o = (a[15:0]) <= (b[15:0]);
|
3'd2: o[63:0] = (a[31:0]) <= (b[31:0]);
|
3'd2: o = (a[31:0]) <= (b[31:0]);
|
3'd3: o[63:0] = (a) <= (b);
|
3'd4: o = {
|
3'd4: o[63:0] = {
|
7'h0,(a[63:56]) <= (b[63:56]),
|
7'h0,(a[7:0]) <= (b[7:0]),
|
|
7'h0,(a[15:8]) <= (b[15:8]),
|
|
7'h0,(a[23:16]) <= (b[23:16]),
|
|
7'h0,(a[31:24]) <= (b[31:24]),
|
|
7'h0,(a[39:32]) <= (b[39:32]),
|
|
7'h0,(a[47:40]) <= (b[47:40]),
|
|
7'h0,(a[55:48]) <= (b[55:48]),
|
7'h0,(a[55:48]) <= (b[55:48]),
|
7'h0,(a[63:56]) <= (b[63:56])
|
7'h0,(a[47:40]) <= (b[47:40]),
|
|
7'h0,(a[39:32]) <= (b[39:32]),
|
|
7'h0,(a[31:24]) <= (b[31:24]),
|
|
7'h0,(a[23:16]) <= (b[23:16]),
|
|
7'h0,(a[15:8]) <= (b[15:8]),
|
|
7'h0,(a[7:0]) <= (b[7:0])
|
};
|
};
|
3'd5: o[63:0] = {
|
3'd5: o = {
|
15'h0,(a[15:0]) <= (b[15:0]),
|
15'h0,(a[63:48]) <= (b[63:48]),
|
15'h0,(a[31:16]) <= (b[31:16]),
|
|
15'h0,(a[47:32]) <= (b[47:32]),
|
15'h0,(a[47:32]) <= (b[47:32]),
|
15'h0,(a[63:48]) <= (b[63:48])
|
15'h0,(a[31:16]) <= (b[31:16]),
|
|
15'h0,(a[15:0]) <= (b[15:0])
|
};
|
};
|
3'd6: o[63:0] = {
|
3'd6: o = {
|
31'h0,(a[31:0]) <= (b[31:0]),
|
31'h0,(a[63:32]) <= (b[63:32]),
|
31'h0,(a[63:32]) <= (b[63:32])
|
31'h0,(a[31:0]) <= (b[31:0])
|
};
|
};
|
3'd7: o[63:0] = (a[63:0]) <= (b[63:0]);
|
3'd7,3'd3: o = (a[63:0]) <= (b[63:0]);
|
endcase
|
endcase
|
`else
|
`else
|
o[63:0] = (a[63:0]) <= (b[63:0]);
|
o[63:0] = (a[63:0]) <= (b[63:0]);
|
`endif
|
`endif
|
end
|
end
|
