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// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2018 Robert Finch, Waterloo
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// \\__/ o\ (C) 2018-2019 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@finitron.ca
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// \/_// robfinch<remove>@finitron.ca
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// ||
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// ||
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//
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//
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// FT64_dcache.v
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// FT64_dcache.v
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module FT64_dcache(rst, dce, wclk, wr, sel, wadr, whit, i, li, rclk, rdsize, radr, o, lo, rhit);
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module FT64_dcache(rst, dce, wclk, wr, sel, wadr, whit, i, li, rclk, rdsize, radr, o, lo, rhit);
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input rst;
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input rst;
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input dce; // data cache enable
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input dce; // data cache enable
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input wclk;
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input wclk;
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input wr;
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input wr;
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input [7:0] sel;
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input [31:0] sel;
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input [37:0] wadr;
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input [37:0] wadr;
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output whit;
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output whit;
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input [63:0] i;
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input [255:0] i;
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input [255:0] li; // line input
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input [255:0] li; // line input
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input rclk;
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input rclk;
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input [2:0] rdsize;
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input [2:0] rdsize;
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input [37:0] radr;
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input [37:0] radr;
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output reg [63:0] o;
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output reg [63:0] o;
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FT64_dcache_tag u3
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FT64_dcache_tag u3
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(
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(
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.wclk(wclk),
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.wclk(wclk),
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.dce(dce),
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.dce(dce),
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.wr(wr && wadr[4:3]==2'b11),
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.wr(wr),
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.wadr(wadr),
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.wadr(wadr),
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.rclk(rclk),
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.rclk(rclk),
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.radr(radr),
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.radr(radr),
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.whit(whit),
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.whit(whit),
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.rhit(rhita)
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.rhit(rhita)
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module dcache_mem(rst, clka, ena, wea, addra, dina, clkb, enb, addrb, doutb, ov);
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module dcache_mem(rst, clka, ena, wea, addra, dina, clkb, enb, addrb, doutb, ov);
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input rst;
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input rst;
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input clka;
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input clka;
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input ena;
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input ena;
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input [7:0] wea;
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input [31:0] wea;
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input [13:0] addra;
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input [13:0] addra;
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input [63:0] dina;
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input [255:0] dina;
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input clkb;
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input clkb;
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input enb;
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input enb;
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input [13:0] addrb;
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input [13:0] addrb;
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output reg [255:0] doutb;
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output reg [255:0] doutb;
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output reg [31:0] ov;
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output reg [31:0] ov;
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valid[n] = 32'h00;
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valid[n] = 32'h00;
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end
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end
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genvar g;
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genvar g;
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generate begin
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generate begin
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for (g = 0; g < 4; g = g + 1)
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for (g = 0; g < 32; g = g + 1)
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always @(posedge clka)
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always @(posedge clka)
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begin
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begin
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if (ena & wea[0] & addra[4:3]==g) mem[addra[13:5]][g*64+7:g*64] <= dina[7:0];
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if (ena & wea[g]) mem[addra[13:5]][g*8+7:g*8] <= dina[g*8+7:g*8];
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if (ena & wea[1] & addra[4:3]==g) mem[addra[13:5]][g*64+15:g*64+8] <= dina[15:8];
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if (ena & wea[g]) valid[addra[13:5]][g] <= 1'b1;
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if (ena & wea[2] & addra[4:3]==g) mem[addra[13:5]][g*64+23:g*64+16] <= dina[23:16];
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if (ena & wea[3] & addra[4:3]==g) mem[addra[13:5]][g*64+31:g*64+24] <= dina[31:24];
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if (ena & wea[4] & addra[4:3]==g) mem[addra[13:5]][g*64+39:g*64+32] <= dina[39:32];
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if (ena & wea[5] & addra[4:3]==g) mem[addra[13:5]][g*64+47:g*64+40] <= dina[47:40];
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if (ena & wea[6] & addra[4:3]==g) mem[addra[13:5]][g*64+55:g*64+48] <= dina[55:48];
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if (ena & wea[7] & addra[4:3]==g) mem[addra[13:5]][g*64+63:g*64+56] <= dina[63:56];
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if (ena & wea[0] & addra[4:3]==g) valid[addra[13:5]][g*8] <= 1'b1;
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if (ena & wea[1] & addra[4:3]==g) valid[addra[13:5]][g*8+1] <= 1'b1;
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if (ena & wea[2] & addra[4:3]==g) valid[addra[13:5]][g*8+2] <= 1'b1;
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if (ena & wea[3] & addra[4:3]==g) valid[addra[13:5]][g*8+3] <= 1'b1;
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if (ena & wea[4] & addra[4:3]==g) valid[addra[13:5]][g*8+4] <= 1'b1;
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if (ena & wea[5] & addra[4:3]==g) valid[addra[13:5]][g*8+5] <= 1'b1;
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if (ena & wea[6] & addra[4:3]==g) valid[addra[13:5]][g*8+6] <= 1'b1;
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if (ena & wea[7] & addra[4:3]==g) valid[addra[13:5]][g*8+7] <= 1'b1;
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end
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end
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end
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end
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endgenerate
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endgenerate
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always @(posedge clkb)
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always @(posedge clkb)
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if (enb)
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if (enb)
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