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[/] [thor/] [trunk/] [FT64v7/] [rtl/] [common/] [FT64_icache.v] - Diff between revs 61 and 66

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Rev 61 Rev 66
Line 373... Line 373... 
wire taghit;
 
wire taghit;
 
reg wr1,wr2;
 
reg wr1,wr2;
 
reg [9:0] en1, en2;
 
reg [9:0] en1, en2;
 
reg invline1, invline2;
 
reg invline1, invline2;
 
 
 
 
 
 
 
wire iclk;
 
 
 
BUFH ucb1 (.I(clk), .O(iclk));
 
 
 
 
 
// Must update the cache memory on the cycle after a write to the tag memmory.
 
// Must update the cache memory on the cycle after a write to the tag memmory.
 
// Otherwise lineno won't be valid. Tag memory takes two clock cycles to update.
 
// Otherwise lineno won't be valid. Tag memory takes two clock cycles to update.
 
always @(posedge clk)
 
always @(posedge iclk)
 
        wr1 <= wr;
 
        wr1 <= wr;
 
always @(posedge clk)
 
always @(posedge iclk)
 
        wr2 <= wr1;
 
        wr2 <= wr1;
 
always @(posedge clk)
 
always @(posedge iclk)
 
        i1 <= i[305:0];
 
        i1 <= i[305:0];
 
always @(posedge clk)
 
always @(posedge iclk)
 
        i2 <= i1;
 
        i2 <= i1;
 
always @(posedge clk)
 
always @(posedge iclk)
 
        en1 <= en;
 
        en1 <= en;
 
always @(posedge clk)
 
always @(posedge iclk)
 
        en2 <= en1;
 
        en2 <= en1;
 
always @(posedge clk)
 
always @(posedge iclk)
 
        invline1 <= invline;
 
        invline1 <= invline;
 
always @(posedge clk)
 
always @(posedge iclk)
 
        invline2 <= invline1;
 
        invline2 <= invline1;
 
 
 
 
 
generate begin : tags
 
generate begin : tags
 
if (FOURWAY) begin
 
if (FOURWAY) begin
 
 
 
 
 
FT64_L1_icache_mem #(.pLines(pLines)) u1
 
FT64_L1_icache_mem #(.pLines(pLines)) u1
 
(
 
(
 
    .rst(rst),
 
    .rst(rst),
 
    .clk(clk),
 
    .clk(iclk),
 
    .wr(wr1),
 
    .wr(wr1),
 
    .en(en1),
 
    .en(en1),
 
    .i(i1),
 
    .i(i1),
 
    .lineno(lineno),
 
    .lineno(lineno),
 
    .o(ic),
 
    .o(ic),
Line 412... Line 415... 
);
 
);
 
 
 
 
 
FT64_L1_icache_cmptag4way #(.pLines(pLines)) u3
 
FT64_L1_icache_cmptag4way #(.pLines(pLines)) u3
 
(
 
(
 
        .rst(rst),
 
        .rst(rst),
 
        .clk(clk),
 
        .clk(iclk),
 
        .nxt(nxt),
 
        .nxt(nxt),
 
        .wr(wr),
 
        .wr(wr),
 
        .adr(adr),
 
        .adr(adr),
 
        .lineno(lineno),
 
        .lineno(lineno),
 
        .hit(taghit)
 
        .hit(taghit)
Line 425... Line 428... 
else if (CAMTAGS) begin
 
else if (CAMTAGS) begin
 
 
 
 
 
FT64_L1_icache_mem u1
 
FT64_L1_icache_mem u1
 
(
 
(
 
    .rst(rst),
 
    .rst(rst),
 
    .clk(clk),
 
    .clk(iclk),
 
    .wr(wr2),
 
    .wr(wr2),
 
    .en(en2),
 
    .en(en2),
 
    .i(i2),
 
    .i(i2),
 
    .lineno(lineno),
 
    .lineno(lineno),
 
    .o(ic),
 
    .o(ic),
Line 439... Line 442... 
);
 
);
 
 
 
 
 
FT64_L1_icache_camtag u2
 
FT64_L1_icache_camtag u2
 
(
 
(
 
    .rst(rst),
 
    .rst(rst),
 
    .clk(clk),
 
    .clk(iclk),
 
    .nxt(nxt),
 
    .nxt(nxt),
 
    .wlineno(wlineno),
 
    .wlineno(wlineno),
 
    .wadr(wadr),
 
    .wadr(wadr),
 
    .wr(wr),
 
    .wr(wr),
 
    .adr(adr),
 
    .adr(adr),
Line 536... Line 539... 
// Otherwise the line number would change in the middle of the line. The
 
// Otherwise the line number would change in the middle of the line. The
 
// first half of the line load is signified by an even hexibyte address (
 
// first half of the line load is signified by an even hexibyte address (
 
// address bit 4).
 
// address bit 4).
 
// -----------------------------------------------------------------------------
 
// -----------------------------------------------------------------------------
 
 
 
 
 
module FT64_L2_icache(rst, clk, nxt, wr, wr_ack, rd_ack, xsel, adr, cnt, exv_i, i, err_i, o, hit, invall, invline);
 
module FT64_L2_icache(rst, clk, nxt, wr, adr, cnt, exv_i, i, err_i, o, hit, invall, invline);
 
parameter CAMTAGS = 1'b0;   // 32 way
 
parameter CAMTAGS = 1'b0;   // 32 way
 
parameter FOURWAY = 1'b1;
 
parameter FOURWAY = 1'b1;
 
parameter AMSB = 63;
 
parameter AMSB = 63;
 
input rst;
 
input rst;
 
input clk;
 
input clk;
 
input nxt;
 
input nxt;
 
input wr;
 
input wr;
 
output wr_ack;
 
 
 
output rd_ack;
 
 
 
input xsel;
 
 
 
input [AMSB+8:0] adr;
 
input [AMSB+8:0] adr;
 
input [2:0] cnt;
 
input [2:0] cnt;
 
input exv_i;
 
input exv_i;
 
input [63:0] i;
 
input [63:0] i;
 
input err_i;
 
input err_i;
Line 573... Line 573... 
always @(posedge clk)
 
always @(posedge clk)
 
        wr1 <= wr;
 
        wr1 <= wr;
 
always @(posedge clk)
 
always @(posedge clk)
 
        wr2 <= wr1;
 
        wr2 <= wr1;
 
always @(posedge clk)
 
always @(posedge clk)
 
        sel1 <= {xsel,adr[4:3]};
 
        sel1 <= cnt;
 
always @(posedge clk)
 
always @(posedge clk)
 
        sel2 <= sel1;
 
        sel2 <= sel1;
 
always @(posedge clk)
 
always @(posedge clk)
 
        last_adr <= adr;
 
        last_adr <= adr;
 
always @(posedge clk)
 
always @(posedge clk)
 
        f1 <= {err_i,exv_i};
 
        f1 <= {err_i,exv_i};
 
always @(posedge clk)
 
always @(posedge clk)
 
        f2 <= f1;
 
        f2 <= f1;
 
 
 
 
 
reg [3:0] rdackx;
 
 
 
always @(posedge clk)
 
 
 
if (rst)
 
 
 
        rdackx <= 4'b0;
 
 
 
else begin
 
 
 
        if (last_adr != adr || wr || wr1 || wr2)
 
 
 
                rdackx <= 4'b0;
 
 
 
        else
 
 
 
                rdackx <= {rdackx,~(wr|wr1|wr2)};
 
 
 
end
 
 
 
 
 
 
 
assign rd_ack = rdackx[3] & ~(last_adr!=adr || wr || wr1 || wr2);
 
 
 
 
 
 
 
always @(posedge clk)
 
always @(posedge clk)
 
     i1 <= i;
 
     i1 <= i;
 
always @(posedge clk)
 
always @(posedge clk)
 
     i2 <= i1;
 
     i2 <= i1;
 
 
 
 
Line 655... Line 642... 
);
 
);
 
end
 
end
 
endgenerate
 
endgenerate
 
 
 
 
 
assign hit = taghit & lv;
 
assign hit = taghit & lv;
 
assign wr_ack = wr2;
 
 
 
 
 
 
 
endmodule
 
endmodule
 
 
 
 
 
// Four way set associative tag memory
 
// Four way set associative tag memory
 
module FT64_L2_icache_cmptag4way(rst, clk, nxt, wr, adr, lineno, hit);
 
module FT64_L2_icache_cmptag4way(rst, clk, nxt, wr, adr, lineno, hit);

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