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[/] [thor/] [trunk/] [FT64v7/] [rtl/] [common/] [FT64_pic.v] - Diff between revs 61 and 66

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Rev 61 Rev 66
Line 88... Line 88...
        output nmio,    // normally connected to the nmi of cpu
        output nmio,    // normally connected to the nmi of cpu
        output [7:0] causeo
        output [7:0] causeo
);
);
parameter pIOAddress = 32'hFFDC_0F00;
parameter pIOAddress = 32'hFFDC_0F00;
 
 
 
wire clk;
reg [31:0] trig;
reg [31:0] trig;
reg [31:0] ie;           // interrupt enable register
reg [31:0] ie;           // interrupt enable register
reg rdy1;
reg rdy1;
reg [4:0] irqenc;
reg [4:0] irqenc;
wire [31:0] i = {   i31,i30,i29,i28,i27,i26,i25,i24,i23,i22,i21,i20,i19,i18,i17,i16,
wire [31:0] i = {   i31,i30,i29,i28,i27,i26,i25,i24,i23,i22,i21,i20,i19,i18,i17,i16,
Line 115... Line 116...
end
end
 
 
wire cs = cyc_i && stb_i && adr_i[31:8]==pIOAddress[31:8];
wire cs = cyc_i && stb_i && adr_i[31:8]==pIOAddress[31:8];
assign vol_o = cs;
assign vol_o = cs;
 
 
always @(posedge clk_i)
assign clk = clk_i;
 
//BUFH ucb1 (.I(clk_i), .O(clk));
 
 
 
always @(posedge clk)
        rdy1 <= cs;
        rdy1 <= cs;
assign ack_o = cs ? (wr_i ? 1'b1 : rdy1) : 1'b0;
assign ack_o = cs ? (wr_i ? 1'b1 : rdy1) : 1'b0;
 
 
// write registers      
// write registers      
always @(posedge clk_i)
always @(posedge clk)
        if (rst_i) begin
        if (rst_i) begin
                ie <= 32'h0;
                ie <= 32'h0;
                rste <= 32'h0;
                rste <= 32'h0;
                trig <= 32'h0;
                trig <= 32'h0;
        end
        end
Line 153... Line 157...
                        endcase
                        endcase
                end
                end
        end
        end
 
 
// read registers
// read registers
always @(posedge clk_i)
always @(posedge clk)
begin
begin
        if (irqenc!=5'd0)
        if (irqenc!=5'd0)
                $display("PIC: %d",irqenc);
                $display("PIC: %d",irqenc);
        if (cs)
        if (cs)
                casez (adr_i[7:2])
                casez (adr_i[7:2])
Line 172... Line 176...
assign irqo = (irqenc == 5'h0) ? 4'd0 : irq[irqenc] & {4{ie[irqenc]}};
assign irqo = (irqenc == 5'h0) ? 4'd0 : irq[irqenc] & {4{ie[irqenc]}};
assign causeo = (irqenc == 5'h0) ? 8'd0 : cause[irqenc];
assign causeo = (irqenc == 5'h0) ? 8'd0 : cause[irqenc];
assign nmio = nmii & ie[0];
assign nmio = nmii & ie[0];
 
 
// Edge detect circuit
// Edge detect circuit
always @(posedge clk_i)
always @(posedge clk)
begin
begin
        for (n = 1; n < 32; n = n + 1)
        for (n = 1; n < 32; n = n + 1)
        begin
        begin
                ib[n] <= i[n];
                ib[n] <= i[n];
                if (trig[n]) iedge[n] <= 1'b1;
                if (trig[n]) iedge[n] <= 1'b1;
Line 186... Line 190...
end
end
 
 
// irq requests are latched on every rising clock edge to prevent
// irq requests are latched on every rising clock edge to prevent
// misreads
// misreads
// nmi is not encoded
// nmi is not encoded
always @(posedge clk_i)
always @(posedge clk)
begin
begin
        irqenc <= 5'd0;
        irqenc <= 5'd0;
        for (n = 31; n > 0; n = n - 1)
        for (n = 31; n > 0; n = n - 1)
                if ((es[n] ? iedge[n] : i[n])) irqenc <= n;
                if ((es[n] ? iedge[n] : i[n])) irqenc <= n;
end
end

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