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URL https://opencores.org/ocsvn/uart2bus/uart2bus/trunk

Subversion Repositories uart2bus

[/] [uart2bus/] [trunk/] [verilog/] [bench/] [tb_uart2bus_top.v] - Diff between revs 2 and 12

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Rev 2 Rev 12
Line 135... Line 135...
wire    [7:0]    int_address;    // address bus to register file 
wire    [7:0]    int_address;    // address bus to register file 
wire    [7:0]    int_wr_data;    // write data to register file 
wire    [7:0]    int_wr_data;    // write data to register file 
wire                    int_write;              // write control to register file 
wire                    int_write;              // write control to register file 
wire                    int_read;               // read control to register file 
wire                    int_read;               // read control to register file 
wire    [7:0]    int_rd_data;    // data read from register file 
wire    [7:0]    int_rd_data;    // data read from register file 
 
wire                    int_req;                // bus access request signal 
 
wire                    int_gnt;                // bus access grant signal 
wire                    ser_in;                 // DUT serial input 
wire                    ser_in;                 // DUT serial input 
wire                    ser_out;                // DUT serial output 
wire                    ser_out;                // DUT serial output 
 
 
// DUT instance 
// DUT instance 
uart2bus_top uart2bus1
uart2bus_top uart2bus1
(
(
        .clock(clock), .reset(reset),
        .clock(clock), .reset(reset),
        .ser_in(ser_in), .ser_out(ser_out),
        .ser_in(ser_in), .ser_out(ser_out),
        .int_address(int_address), .int_wr_data(int_wr_data), .int_write(int_write),
        .int_address(int_address), .int_wr_data(int_wr_data), .int_write(int_write),
        .int_rd_data(int_rd_data), .int_read(int_read)
        .int_rd_data(int_rd_data), .int_read(int_read),
 
        .int_req(int_req), .int_gnt(int_gnt)
);
);
 
// bus grant is always active 
 
assign int_gnt = 1'b1;
 
 
// serial interface to test bench 
// serial interface to test bench 
assign ser_in = serial_out;
assign ser_in = serial_out;
always @ (posedge clock) serial_in = ser_out;
always @ (posedge clock) serial_in = ser_out;
 
 

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