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[/] [uart2bus/] [trunk/] [verilog/] [rtl/] [uart_parser.v] - Diff between revs 2 and 12

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Rev 2 Rev 12
Line 10... Line 10...
        // transmit and receive internal interface signals from uart interface 
        // transmit and receive internal interface signals from uart interface 
        rx_data, new_rx_data,
        rx_data, new_rx_data,
        tx_data, new_tx_data, tx_busy,
        tx_data, new_tx_data, tx_busy,
        // internal bus to register file 
        // internal bus to register file 
        int_address, int_wr_data, int_write,
        int_address, int_wr_data, int_write,
        int_rd_data, int_read
        int_rd_data, int_read,
 
        int_req, int_gnt
);
);
//---------------------------------------------------------------------------------------
//---------------------------------------------------------------------------------------
// parameters 
// parameters 
parameter               AW = 8;                 // address bus width parameter 
parameter               AW = 8;                 // address bus width parameter 
 
 
Line 30... Line 31...
output  [AW-1:0] int_address;    // address bus to register file 
output  [AW-1:0] int_address;    // address bus to register file 
output  [7:0]    int_wr_data;    // write data to register file 
output  [7:0]    int_wr_data;    // write data to register file 
output                  int_write;              // write control to register file 
output                  int_write;              // write control to register file 
output                  int_read;               // read control to register file 
output                  int_read;               // read control to register file 
input   [7:0]    int_rd_data;    // data read from register file 
input   [7:0]    int_rd_data;    // data read from register file 
 
output                  int_req;                // bus access request signal 
 
input                   int_gnt;                // bus access grant signal 
 
 
// registered outputs
// registered outputs
reg     [7:0] tx_data;
reg     [7:0] tx_data;
reg new_tx_data;
reg new_tx_data;
reg     [AW-1:0] int_address;
reg     [AW-1:0] int_address;
reg     [7:0] int_wr_data;
reg     [7:0] int_wr_data;
reg int_write, int_read;
reg write_req, read_req, int_write, int_read;
 
 
// internal constants 
// internal constants 
// define characters used by the parser 
// define characters used by the parser 
`define CHAR_CR                 8'h0d
`define CHAR_CR                 8'h0d
`define CHAR_LF                 8'h0a
`define CHAR_LF                 8'h0a
Line 401... Line 404...
// internal write control and data 
// internal write control and data 
always @ (posedge clock or posedge reset)
always @ (posedge clock or posedge reset)
begin
begin
        if (reset)
        if (reset)
        begin
        begin
 
                write_req <= 1'b0;
                int_write <= 1'b0;
                int_write <= 1'b0;
                int_wr_data <= 0;
                int_wr_data <= 0;
        end
        end
        else if (write_op && (main_sm == `MAIN_ADDR) && new_rx_data && !data_in_hex_range)
        else if (write_op && (main_sm == `MAIN_ADDR) && new_rx_data && !data_in_hex_range)
        begin
        begin
                int_write <= 1'b1;
                write_req <= 1'b1;
                int_wr_data <= data_param;
                int_wr_data <= data_param;
        end
        end
        // binary extension mode 
        // binary extension mode 
        else if (bin_write_op && (main_sm == `MAIN_BIN_DATA) && new_rx_data)
        else if (bin_write_op && (main_sm == `MAIN_BIN_DATA) && new_rx_data)
        begin
        begin
                int_write <= 1'b1;
                write_req <= 1'b1;
                int_wr_data <= rx_data;
                int_wr_data <= rx_data;
        end
        end
 
        else if (int_gnt && write_req)
 
        begin
 
                // set internal bus write and clear the write request flag 
 
                int_write <= 1'b1;
 
                write_req <= 1'b0;
 
        end
        else
        else
                int_write <= 1'b0;
                int_write <= 1'b0;
end
end
 
 
// internal read control 
// internal read control 
always @ (posedge clock or posedge reset)
always @ (posedge clock or posedge reset)
begin
begin
        if (reset)
        if (reset)
 
        begin
                int_read <= 1'b0;
                int_read <= 1'b0;
 
                read_req <= 1'b0;
 
        end
        else if (read_op && (main_sm == `MAIN_ADDR) && new_rx_data && !data_in_hex_range)
        else if (read_op && (main_sm == `MAIN_ADDR) && new_rx_data && !data_in_hex_range)
                int_read <= 1'b1;
                read_req <= 1'b1;
        // binary extension 
        // binary extension 
        else if (bin_read_op && (main_sm == `MAIN_BIN_LEN) && new_rx_data)
        else if (bin_read_op && (main_sm == `MAIN_BIN_LEN) && new_rx_data)
                // the first read request is issued on reception of the length byte 
                // the first read request is issued on reception of the length byte 
                int_read <= 1'b1;
                read_req <= 1'b1;
        else if (bin_read_op && tx_end_p && !bin_last_byte)
        else if (bin_read_op && tx_end_p && !bin_last_byte)
                // the next read requests are issued after the previous read value was transmitted and 
                // the next read requests are issued after the previous read value was transmitted and 
                // this is not the last byte to be read.
                // this is not the last byte to be read.
 
                read_req <= 1'b1;
 
        else if (int_gnt && read_req)
 
        begin
 
                // set internal bus read and clear the read request flag 
                int_read <= 1'b1;
                int_read <= 1'b1;
 
                read_req <= 1'b0;
 
        end
        else
        else
                int_read <= 1'b0;
                int_read <= 1'b0;
end
end
 
 
 
// external request signal is active on read or write request 
 
assign int_req = write_req | read_req;
 
 
// internal address 
// internal address 
always @ (posedge clock or posedge reset)
always @ (posedge clock or posedge reset)
begin
begin
        if (reset)
        if (reset)
                int_address <= 0;
                int_address <= 0;
Line 451... Line 473...
        else if ((main_sm == `MAIN_BIN_LEN) && new_rx_data)
        else if ((main_sm == `MAIN_BIN_LEN) && new_rx_data)
                // sample address parameter on reception of length byte 
                // sample address parameter on reception of length byte 
                int_address <= addr_param[AW-1:0];
                int_address <= addr_param[AW-1:0];
        else if (addr_auto_inc &&
        else if (addr_auto_inc &&
                         ((bin_read_op && tx_end_p && !bin_last_byte) ||
                         ((bin_read_op && tx_end_p && !bin_last_byte) ||
//                        (bin_write_op && (main_sm == `MAIN_BIN_DATA) && new_rx_data)))
 
                          (bin_write_op && int_write)))
                          (bin_write_op && int_write)))
                // address is incremented on every read or write if enabled 
                // address is incremented on every read or write if enabled 
                int_address <= int_address + 1;
                int_address <= int_address + 1;
end
end
 
 

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