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[/] [uart2bus/] [trunk/] [vhdl/] [rtl/] [baudGen.vhd] - Diff between revs 11 and 13

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Rev 11 Rev 13
Line 9... Line 9...
--              baud_limit = (global_clock_freq / gcd(global_clock_freq, 16*baud_rate)) - baud_freq 
--              baud_limit = (global_clock_freq / gcd(global_clock_freq, 16*baud_rate)) - baud_freq 
--
--
-----------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------
library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
 
 
entity baudGen is
entity baudGen is
  port ( clr       : in  std_logic;                     -- global reset input
  port ( clr       : in  std_logic;                     -- global reset input
         clk       : in  std_logic;                     -- global clock input
         clk       : in  std_logic;                     -- global clock input
         -- baudFreq = 16 * baudRate / gcd(clkFreq, 16 * baudRate)
         -- baudFreq = 16 * baudRate / gcd(clkFreq, 16 * baudRate)
Line 35... Line 35...
      if (clr = '1') then
      if (clr = '1') then
        counter <= (others => '0');
        counter <= (others => '0');
        ce16 <= '0';
        ce16 <= '0';
      elsif (rising_edge(clk)) then
      elsif (rising_edge(clk)) then
        if (counter >= baudLimit) then
        if (counter >= baudLimit) then
          counter <= counter - baudLimit;
          counter <= std_logic_vector(unsigned(counter) - unsigned(baudLimit));
          ce16 <= '1';
          ce16 <= '1';
        else
        else
          counter <= counter + baudFreq;
          counter <= std_logic_vector(unsigned(counter) + unsigned(baudFreq));
          ce16 <= '0';
          ce16 <= '0';
        end if;
        end if;
      end if;
      end if;
    end process;
    end process;
  end Behavioral;
  end Behavioral;

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