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[/] [udp_ip_stack/] [trunk/] [rtl/] [vhdl/] [ml605/] [UDP_integration_example.vhd] - Diff between revs 6 and 8

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Line 38... Line 38...
                UDP_RX                                                          : out std_logic;
                UDP_RX                                                          : out std_logic;
                UDP_Start                                                       : out std_logic;
                UDP_Start                                                       : out std_logic;
                PBTX_LED                                                                : out std_logic;
                PBTX_LED                                                                : out std_logic;
                TX_Started                                                      : out std_logic;
                TX_Started                                                      : out std_logic;
                TX_Completed                                            : out std_logic;
                TX_Completed                                            : out std_logic;
 
                TX_RSLT_0                                                       : out std_logic;
 
                TX_RSLT_1                                                       : out std_logic;
                reset_leds                                                      : in std_logic;
                reset_leds                                                      : in std_logic;
      display                           : out std_logic_vector(7 downto 0);
      display                           : out std_logic_vector(7 downto 0);
 
 
      -- GMII Interface
      -- GMII Interface
      -----------------     
      -----------------     
Line 64... Line 66...
 
 
  ------------------------------------------------------------------------------
  ------------------------------------------------------------------------------
  -- Component Declaration for the complete IP layer
  -- Component Declaration for the complete IP layer
  ------------------------------------------------------------------------------
  ------------------------------------------------------------------------------
component UDP_Complete
component UDP_Complete
 
         generic (
 
                        CLOCK_FREQ                      : integer := 125000000;                                                 -- freq of data_in_clk -- needed to timout cntr
 
                        ARP_TIMEOUT                     : integer := 60                                                                 -- ARP response timeout (s)
 
                        );
    Port (
    Port (
                        -- UDP TX signals
                        -- UDP TX signals
                        udp_tx_start                    : in std_logic;                                                 -- indicates req to tx UDP
                        udp_tx_start                    : in std_logic;                                                 -- indicates req to tx UDP
                        udp_txi                                 : in udp_tx_type;                                                       -- UDP tx cxns
                        udp_txi                                 : in udp_tx_type;                                                       -- UDP tx cxns
                        udp_tx_result                   : out std_logic_vector (1 downto 0);-- tx status (changes during transmission)
                        udp_tx_result                   : out std_logic_vector (1 downto 0);-- tx status (changes during transmission)
Line 82... Line 88...
                        clk_in_n             : in  std_logic;
                        clk_in_n             : in  std_logic;
                        clk_out                                 : out std_logic;
                        clk_out                                 : out std_logic;
                        reset                                   : in  STD_LOGIC;
                        reset                                   : in  STD_LOGIC;
                        our_ip_address          : in STD_LOGIC_VECTOR (31 downto 0);
                        our_ip_address          : in STD_LOGIC_VECTOR (31 downto 0);
                        our_mac_address                 : in std_logic_vector (47 downto 0);
                        our_mac_address                 : in std_logic_vector (47 downto 0);
 
                        control                                 : in udp_control_type;
                        -- status signals
                        -- status signals
                        arp_pkt_count                   : out STD_LOGIC_VECTOR(7 downto 0);                      -- count of arp pkts received
                        arp_pkt_count                   : out STD_LOGIC_VECTOR(7 downto 0);                      -- count of arp pkts received
                        ip_pkt_count                    : out STD_LOGIC_VECTOR(7 downto 0);                      -- number of IP pkts received for us
                        ip_pkt_count                    : out STD_LOGIC_VECTOR(7 downto 0);                      -- number of IP pkts received for us
                        -- GMII Interface
                        -- GMII Interface
                        phy_resetn           : out std_logic;
                        phy_resetn           : out std_logic;
Line 102... Line 109...
                        mii_tx_clk           : in  std_logic
                        mii_tx_clk           : in  std_logic
                        );
                        );
end component;
end component;
 
 
 
 
        type state_type is (IDLE, DATA_OUT);
        type state_type is (IDLE, WAIT_RX_DONE, DATA_OUT);
        type count_mode_type is (RST, INCR, HOLD);
        type count_mode_type is (RST, INCR, HOLD);
        type set_clr_type is (SET, CLR, HOLD);
        type set_clr_type is (SET, CLR, HOLD);
 
 
        -- system signals
        -- system signals
        signal clk_int                                                  : std_logic;
        signal clk_int                                                  : std_logic;
Line 127... Line 134...
        signal count                                                    : unsigned (7 downto 0);
        signal count                                                    : unsigned (7 downto 0);
        signal tx_hdr                                                   : udp_tx_header_type;
        signal tx_hdr                                                   : udp_tx_header_type;
        signal tx_start_reg                                     : std_logic;
        signal tx_start_reg                                     : std_logic;
        signal tx_started_reg                           : std_logic;
        signal tx_started_reg                           : std_logic;
        signal tx_fin_reg                                               : std_logic;
        signal tx_fin_reg                                               : std_logic;
        signal udp_rx_start_reg                         : std_logic;
 
 
 
        -- control signals
        -- control signals
        signal next_state                                               : state_type;
        signal next_state                                               : state_type;
        signal set_state                                                : std_logic;
        signal set_state                                                : std_logic;
        signal set_count                                                : count_mode_type;
        signal set_count                                                : count_mode_type;
        signal set_hdr                                                  : std_logic;
        signal set_hdr                                                  : std_logic;
        signal set_tx_start                                     : set_clr_type;
        signal set_tx_start                                     : set_clr_type;
        signal set_last                                         : std_logic;
        signal set_last                                         : std_logic;
        signal set_tx_started                           : set_clr_type;
        signal set_tx_started                           : set_clr_type;
        signal set_tx_fin                                               : set_clr_type;
        signal set_tx_fin                                               : set_clr_type;
        signal set_udp_rx_start_reg             : set_clr_type;
 
        signal first_byte_rx                                    : STD_LOGIC_VECTOR(7 downto 0);
        signal first_byte_rx                                    : STD_LOGIC_VECTOR(7 downto 0);
 
        signal control_int                                      : udp_control_type;
 
 
begin
begin
 
 
        process (
        process (
                our_ip, our_mac, udp_rx_int, udp_tx_start_int, udp_rx_start_int, ip_rx_hdr_int, udp_rx_start_reg,
                our_ip, our_mac, udp_tx_result_int, udp_rx_int, udp_tx_start_int, udp_rx_start_int, ip_rx_hdr_int,
                udp_tx_int, count, clk_int, ip_pkt_count_int, arp_pkt_count_int,
                udp_tx_int, count, clk_int, ip_pkt_count_int, arp_pkt_count_int,
                reset, tx_started_reg, tx_fin_reg, tx_start_reg
                reset, tx_started_reg, tx_fin_reg, tx_start_reg
                )
                )
        begin
        begin
                -- set up our local addresses
                -- set up our local addresses and default controls
                our_ip  <= x"c0a80509";         -- 192.168.5.9
                our_ip  <= x"c0a80509";         -- 192.168.5.9
                our_mac         <= x"002320212223";
                our_mac         <= x"002320212223";
 
                control_int.ip_controls.arp_controls.clear_cache <= '0';
 
 
                -- determine RX good and error LEDs
                -- determine RX good and error LEDs
                if udp_rx_int.hdr.is_valid = '1' then
                if udp_rx_int.hdr.is_valid = '1' then
                        UDP_RX <= '1';
                        UDP_RX <= '1';
                else
                else
                        UDP_RX <= '0';
                        UDP_RX <= '0';
                end if;
                end if;
 
 
                UDP_Start <= udp_rx_start_reg;
                UDP_Start <= udp_rx_start_int;
                TX_Started <= tx_start_reg; --tx_started_reg;
                TX_Started <= tx_start_reg; --tx_started_reg;
                TX_Completed <= tx_fin_reg;
                TX_Completed <= tx_fin_reg;
 
                TX_RSLT_0 <= udp_tx_result_int(0);
 
                TX_RSLT_1 <= udp_tx_result_int(1);
 
 
                -- set display leds to show IP pkt rx count on 7..4 and arp rx count on 3..0
                -- set display leds to show IP pkt rx count on 7..4 and arp rx count on 3..0
                display (7 downto 4) <= ip_pkt_count_int (3 downto 0);
                display (7 downto 4) <= ip_pkt_count_int (3 downto 0);
                display (3 downto 0) <= arp_pkt_count_int (3 downto 0);
 
 
--              display (3 downto 0) <= arp_pkt_count_int (3 downto 0);
 
                case state is
 
                        when IDLE                       => display (3 downto 0) <= "0001";
 
                        when WAIT_RX_DONE => display (3 downto 0) <= "0010";
 
                        when DATA_OUT           => display (3 downto 0) <= "0011";
 
                end case;
 
 
        end process;
        end process;
 
 
        -- AUTO TX process - on receipt of any UDP pkt, send a response,
        -- AUTO TX process - on receipt of any UDP pkt, send a response. data sent is modified if a broadcast was received.
 
 
        -- TX response process - COMB
        -- TX response process - COMB
   tx_proc_combinatorial: process(
   tx_proc_combinatorial: process(
                -- inputs
                -- inputs
                udp_rx_start_int, udp_tx_data_out_ready_int, udp_tx_int.data.data_out_valid,
                udp_rx_start_int, udp_rx_int, udp_tx_data_out_ready_int, udp_tx_result_int, ip_rx_hdr_int,
                udp_rx_int, PBTX, reset_leds,
                udp_tx_int.data.data_out_valid, PBTX,
                -- state
                -- state
                state, count, tx_hdr, tx_start_reg, tx_started_reg, tx_fin_reg, udp_rx_start_reg,
                state, count, tx_hdr, tx_start_reg, tx_started_reg, tx_fin_reg,
                -- controls
                -- controls
                next_state, set_state, set_count, set_hdr, set_tx_start, set_last,
                next_state, set_state, set_count, set_hdr, set_tx_start, set_last,
                set_tx_started, set_tx_fin, set_udp_rx_start_reg, first_byte_rx
                set_tx_started, set_tx_fin, first_byte_rx
                )
                )
   begin
   begin
                -- set output_followers
                -- set output_followers
                udp_tx_int.hdr <= tx_hdr;
                udp_tx_int.hdr <= tx_hdr;
                udp_tx_int.data.data_out_last <= set_last;
                udp_tx_int.data.data_out_last <= set_last;
Line 198... Line 213...
                set_hdr <= '0';
                set_hdr <= '0';
                set_tx_start <= HOLD;
                set_tx_start <= HOLD;
                set_last <= '0';
                set_last <= '0';
                set_tx_started <= HOLD;
                set_tx_started <= HOLD;
                set_tx_fin <= HOLD;
                set_tx_fin <= HOLD;
                set_udp_rx_start_reg <= HOLD;
 
                first_byte_rx <= (others => '0');
                first_byte_rx <= (others => '0');
 
                udp_tx_int.data.data_out <= (others => '0');
 
                udp_tx_int.data.data_out_valid <= '0';
 
 
                -- FSM
                -- FSM
                case state is
                case state is
 
 
                        when IDLE =>
                        when IDLE =>
                                udp_tx_int.data.data_out <= (others => '0');
 
                                udp_tx_int.data.data_out_valid <= '0';
                                udp_tx_int.data.data_out_valid <= '0';
                                if udp_rx_start_int = '1' or PBTX = '1' then
                                if udp_rx_start_int = '1' or PBTX = '1' then
                                        if udp_rx_start_int = '1' then
                                        if udp_rx_start_int = '1' then
                                                first_byte_rx <= udp_rx_int.data.data_in;
                                                first_byte_rx <= udp_rx_int.data.data_in;
                                        else
                                        else
                                                first_byte_rx <= x"00";
                                                first_byte_rx <= x"00";
                                        end if;
                                        end if;
                                        set_udp_rx_start_reg <= SET;
 
                                        set_tx_started <= SET;
 
                                        set_hdr <= '1';
 
                                        set_tx_start <= SET;
 
                                        set_tx_fin <= CLR;
                                        set_tx_fin <= CLR;
                                        set_count <= RST;
                                        set_count <= RST;
 
                                        set_hdr <= '1';
 
                                        if udp_rx_int.data.data_in_last = '1' then
 
                                                set_tx_started <= SET;
 
                                                set_tx_start <= SET;
 
                                                next_state <= DATA_OUT;
 
                                                set_state <= '1';
 
                                        else
 
                                                next_state <= WAIT_RX_DONE;
 
                                                set_state <= '1';
 
                                        end if;
 
                                end if;
 
 
 
                        when WAIT_RX_DONE =>
 
                                -- wait until RX pkt fully received
 
                                if udp_rx_int.data.data_in_last = '1' then
 
                                        set_tx_started <= SET;
 
                                        set_tx_start <= SET;
                                        next_state <= DATA_OUT;
                                        next_state <= DATA_OUT;
                                        set_state <= '1';
                                        set_state <= '1';
                                elsif reset_leds = '1' then
 
                                        set_udp_rx_start_reg <= CLR;
 
                                        set_tx_started <= CLR;
 
                                        set_tx_fin <= CLR;
 
                                end if;
                                end if;
 
 
                        when DATA_OUT =>
                        when DATA_OUT =>
 
                                if udp_tx_result_int = UDPTX_RESULT_ERR then
 
                                        -- have an error from the IP TX layer, clear down the TX
 
                                        set_tx_start <= CLR;
 
                                        set_tx_fin <= SET;
 
                                        set_tx_started <= CLR;
 
                                        next_state <= IDLE;
 
                                        set_state <= '1';
 
                                else
 
                                        if udp_tx_result_int = UDPTX_RESULT_SENDING then
 
                                                set_tx_start <= CLR;            -- reset out start req as soon as we know we are sending
 
                                        end if;
 
                                        if ip_rx_hdr_int.is_broadcast = '1' then
 
                                                udp_tx_int.data.data_out <= std_logic_vector(count) or x"50";
 
                                        else
                                udp_tx_int.data.data_out <= std_logic_vector(count) or x"40";
                                udp_tx_int.data.data_out <= std_logic_vector(count) or x"40";
 
                                        end if;
                                udp_tx_int.data.data_out_valid <= udp_tx_data_out_ready_int;
                                udp_tx_int.data.data_out_valid <= udp_tx_data_out_ready_int;
                                if udp_tx_data_out_ready_int = '1' then
                                if udp_tx_data_out_ready_int = '1' then
                                        set_tx_start <= CLR;
 
                                        if unsigned(count) = x"03" then
                                        if unsigned(count) = x"03" then
                                                set_last <= '1';
                                                set_last <= '1';
                                                set_tx_fin <= SET;
                                                set_tx_fin <= SET;
                                                set_tx_started <= CLR;
                                                set_tx_started <= CLR;
                                                next_state <= IDLE;
                                                next_state <= IDLE;
                                                set_state <= '1';
                                                set_state <= '1';
                                        else
                                        else
                                                set_count <= INCR;
                                                set_count <= INCR;
                                        end if;
                                        end if;
                                end if;
                                end if;
 
                                end if;
 
 
                end case;
                end case;
        end process;
        end process;
 
 
 
 
Line 286... Line 325...
 
 
                                -- set tx hdr
                                -- set tx hdr
                                if set_hdr = '1' then
                                if set_hdr = '1' then
                                        -- if the first byte of the rx pkt is 'B' then send to broadcast, otherwise send to reply IP
                                        -- if the first byte of the rx pkt is 'B' then send to broadcast, otherwise send to reply IP
                                        if first_byte_rx = x"42" then
                                        if first_byte_rx = x"42" then
                                                tx_hdr.dst_ip_addr <= IP_BC_ADDR;
                                                tx_hdr.dst_ip_addr <= IP_BC_ADDR;       -- send to Broadcast addr
 
                                        elsif first_byte_rx = x"43" then
 
                                                tx_hdr.dst_ip_addr <= x"c0bbccdd";      -- set dst unknown so get ARP timeout
                                        else
                                        else
                                                tx_hdr.dst_ip_addr <= udp_rx_int.hdr.src_ip_addr;
                                                tx_hdr.dst_ip_addr <= udp_rx_int.hdr.src_ip_addr;       -- reply to sender
                                        end if;
                                        end if;
                                        tx_hdr.dst_port <= udp_rx_int.hdr.src_port;
                                        tx_hdr.dst_port <= udp_rx_int.hdr.src_port;
                                        tx_hdr.src_port <= udp_rx_int.hdr.dst_port;
                                        tx_hdr.src_port <= udp_rx_int.hdr.dst_port;
                                        tx_hdr.data_length <= x"0004";
                                        tx_hdr.data_length <= x"0004";
                                        tx_hdr.checksum <= x"0000";
                                        tx_hdr.checksum <= x"0000";
Line 319... Line 360...
                                        when SET  => tx_fin_reg <= '1';
                                        when SET  => tx_fin_reg <= '1';
                                        when CLR  => tx_fin_reg <= '0';
                                        when CLR  => tx_fin_reg <= '0';
                                        when HOLD => tx_fin_reg <= tx_fin_reg;
                                        when HOLD => tx_fin_reg <= tx_fin_reg;
                                end case;
                                end case;
 
 
                                -- set UDP START signal
 
                                case set_udp_rx_start_reg is
 
                                        when SET  => udp_rx_start_reg <= '1';
 
                                        when CLR  => udp_rx_start_reg <= '0';
 
                                        when HOLD => udp_rx_start_reg <= udp_rx_start_reg;
 
                                end case;
 
 
 
 
 
                        end if;
                        end if;
                end if;
                end if;
 
 
        end process;
        end process;
 
 
 
 
 
 
   ------------------------------------------------------------------------------
   ------------------------------------------------------------------------------
   -- Instantiate the UDP layer
   -- Instantiate the UDP layer
   ------------------------------------------------------------------------------
   ------------------------------------------------------------------------------
    UDP_block : UDP_Complete PORT MAP
    UDP_block : UDP_Complete
                (
                generic map (
 
                                ARP_TIMEOUT             => 30           -- timeout in seconds
 
                         )
 
                PORT MAP (
                                -- UDP interface
                                -- UDP interface
                                udp_tx_start                    => udp_tx_start_int,
                                udp_tx_start                    => udp_tx_start_int,
                                udp_txi                                         => udp_tx_int,
                                udp_txi                                         => udp_tx_int,
                                udp_tx_result                   => udp_tx_result_int,
                                udp_tx_result                   => udp_tx_result_int,
                                udp_tx_data_out_ready=> udp_tx_data_out_ready_int,
                                udp_tx_data_out_ready=> udp_tx_data_out_ready_int,
Line 354... Line 392...
                                clk_in_n             => clk_in_n,
                                clk_in_n             => clk_in_n,
                                clk_out                                 => clk_int,
                                clk_out                                 => clk_int,
                                reset                                   => reset,
                                reset                                   => reset,
                                our_ip_address          => our_ip,
                                our_ip_address          => our_ip,
                                our_mac_address                 => our_mac,
                                our_mac_address                 => our_mac,
 
                                control                                 => control_int,
                                -- status signals
                                -- status signals
                                arp_pkt_count                   => arp_pkt_count_int,
                                arp_pkt_count                   => arp_pkt_count_int,
                                ip_pkt_count                    => ip_pkt_count_int,
                                ip_pkt_count                    => ip_pkt_count_int,
                                -- GMII Interface
                                -- GMII Interface
                                -----------------     
                                -----------------     

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