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[/] [udp_ip_stack/] [trunk/] [rtl/] [vhdl/] [tx_arbitrator.vhd] - Diff between revs 2 and 4

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Line 14... Line 14...
-- Dependencies: 
-- Dependencies: 
--
--
-- Revision: 
-- Revision: 
-- Revision 0.01 - File Created
-- Revision 0.01 - File Created
-- Revision 0.02 - Made sticky on port M1 to optimise access on this port and allow immediate grant
-- Revision 0.02 - Made sticky on port M1 to optimise access on this port and allow immediate grant
 
-- Revision 0.03 - Added first
-- Additional Comments: 
-- Additional Comments: 
--
--
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
library IEEE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_1164.ALL;
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                req_1                           : in  std_logic;
                req_1                           : in  std_logic;
                grant_1                 : out std_logic;
                grant_1                 : out std_logic;
      data_1         : in  std_logic_vector(7 downto 0); -- data byte to tx
      data_1         : in  std_logic_vector(7 downto 0); -- data byte to tx
      valid_1        : in  std_logic;                                                   -- tdata is valid
      valid_1        : in  std_logic;                                                   -- tdata is valid
 
      first_1        : in  std_logic;                                                   -- indicates first byte of frame
      last_1         : in  std_logic;                                                   -- indicates last byte of frame
      last_1         : in  std_logic;                                                   -- indicates last byte of frame
 
 
                req_2                           : in  std_logic;
                req_2                           : in  std_logic;
                grant_2                 : out std_logic;
                grant_2                 : out std_logic;
      data_2         : in  std_logic_vector(7 downto 0); -- data byte to tx
      data_2         : in  std_logic_vector(7 downto 0); -- data byte to tx
      valid_2        : in  std_logic;                                                   -- tdata is valid
      valid_2        : in  std_logic;                                                   -- tdata is valid
 
      first_2        : in  std_logic;                                                   -- indicates first byte of frame
      last_2         : in  std_logic;                                                   -- indicates last byte of frame
      last_2         : in  std_logic;                                                   -- indicates last byte of frame
 
 
      data              : out  std_logic_vector(7 downto 0);     -- data byte to tx
      data              : out  std_logic_vector(7 downto 0);     -- data byte to tx
      valid             : out  std_logic;                                                       -- tdata is valid
      valid             : out  std_logic;                                                       -- tdata is valid
 
      first             : out  std_logic;                                                       -- indicates first byte of frame
      last              : out  std_logic                                                        -- indicates last byte of frame
      last              : out  std_logic                                                        -- indicates last byte of frame
    );
    );
end tx_arbitrator;
end tx_arbitrator;
 
 
architecture Behavioral of tx_arbitrator is
architecture Behavioral of tx_arbitrator is
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        signal grant :  grant_type;
        signal grant :  grant_type;
 
 
begin
begin
        combinatorial : process (
        combinatorial : process (
                grant,
                grant,
                data_1, valid_1, last_1,
                data_1, valid_1, first_1, last_1,
                data_2, valid_2, last_2
                data_2, valid_2, first_2, last_2
                )
                )
        begin
        begin
                -- grant outputs
                -- grant outputs
                case grant is
                case grant is
                        when M1 =>
                        when M1 =>
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                -- multiplexer
                -- multiplexer
                if grant = M1 then
                if grant = M1 then
                        data <= data_1;
                        data <= data_1;
                        valid <= valid_1;
                        valid <= valid_1;
 
                        first <= first_1;
                        last <= last_1;
                        last <= last_1;
                else
                else
                        data <= data_2;
                        data <= data_2;
                        valid <= valid_2;
                        valid <= valid_2;
 
                        first <= first_2;
                        last <= last_2;
                        last <= last_2;
                end if;
                end if;
        end process;
        end process;
 
 
        sequential : process (clk, reset, req_1, req_2, grant)
        sequential : process (clk, reset, req_1, req_2, grant)

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