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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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`ifdef MULTS
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// signed multiplication
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// signed multiplication
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module vl_mults (a,b,p);
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`define MODULE mults
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module `BASE`MODULE (a,b,p);
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`undef MODULE
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parameter operand_a_width = 18;
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parameter operand_a_width = 18;
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parameter operand_b_width = 18;
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parameter operand_b_width = 18;
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parameter result_hi = 35;
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parameter result_hi = 35;
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parameter result_lo = 0;
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parameter result_lo = 0;
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input [operand_a_width-1:0] a;
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input [operand_a_width-1:0] a;
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assign bi = b;
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assign bi = b;
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assign result = ai * bi;
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assign result = ai * bi;
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assign p = result[result_hi:result_lo];
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assign p = result[result_hi:result_lo];
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endmodule
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endmodule
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`endif
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module vl_mults18x18 (a,b,p);
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`ifdef MULTS18X18
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`define MODULE mults18x18
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module `BASE`MODULE (a,b,p);
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`undef MODULE
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input [17:0] a,b;
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input [17:0] a,b;
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output [35:0] p;
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output [35:0] p;
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vl_mult
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vl_mult
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# (.operand_a_width(18), .operand_b_width(18))
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# (.operand_a_width(18), .operand_b_width(18))
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mult0 (.a(a), .b(b), .p(p));
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mult0 (.a(a), .b(b), .p(p));
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endmodule
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endmodule
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`endif
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`ifdef MULT
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`define MODULE mult
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// unsigned multiplication
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// unsigned multiplication
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module vl_mult (a,b,p);
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module `BASE`MODULE (a,b,p);
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`undef MODULE
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parameter operand_a_width = 18;
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parameter operand_a_width = 18;
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parameter operand_b_width = 18;
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parameter operand_b_width = 18;
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parameter result_hi = 35;
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parameter result_hi = 35;
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parameter result_lo = 0;
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parameter result_lo = 0;
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input [operand_a_width-1:0] a;
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input [operand_a_width-1:0] a;
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assign result = a * b;
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assign result = a * b;
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assign p = result[result_hi:result_lo];
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assign p = result[result_hi:result_lo];
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endmodule
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endmodule
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`endif
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`ifdef SHIFT_UNIT_32
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`define MODULE shift_unit_32
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// shift unit
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// shift unit
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// supporting the following shift functions
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// supporting the following shift functions
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// SLL
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// SLL
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// SRL
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// SRL
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// SRA
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// SRA
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`define SHIFT_UNIT_MULT # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7))
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`define SHIFT_UNIT_MULT # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7))
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module vl_shift_unit_32( din, s, dout, opcode);
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module `BASE`MODULE( din, s, dout, opcode);
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`undef MODULE
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input [31:0] din; // data in operand
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input [31:0] din; // data in operand
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input [4:0] s; // shift operand
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input [4:0] s; // shift operand
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input [1:0] opcode;
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input [1:0] opcode;
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output [31:0] dout;
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output [31:0] dout;
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assign sign[3] = din[31] & sra;
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assign sign[3] = din[31] & sra;
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assign sign[2] = sign[3] & (&din[31:24]);
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assign sign[2] = sign[3] & (&din[31:24]);
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assign sign[1] = sign[2] & (&din[23:16]);
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assign sign[1] = sign[2] & (&din[23:16]);
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assign sign[0] = sign[1] & (&din[15:8]);
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assign sign[0] = sign[1] & (&din[15:8]);
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vl_mults `SHIFT_UNIT_MULT mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3]));
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`define MODULE mults
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vl_mults `SHIFT_UNIT_MULT mult_byte2 ( .a({sign[2], din[31:24] ,din[23:16], din[15:8]}), .b({1'b0,s1}), .p(tmp[2]));
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`BASE`MODULE `SHIFT_UNIT_MULT mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3]));
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vl_mults `SHIFT_UNIT_MULT mult_byte1 ( .a({sign[1], din[23:16] ,din[15:8], din[7:0]}), .b({1'b0,s1}), .p(tmp[1]));
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`BASE`MODULE `SHIFT_UNIT_MULT mult_byte2 ( .a({sign[2], din[31:24] ,din[23:16], din[15:8]}), .b({1'b0,s1}), .p(tmp[2]));
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vl_mults `SHIFT_UNIT_MULT mult_byte0 ( .a({sign[0], din[15:8] ,din[7:0], 8'h00}), .b({1'b0,s1}), .p(tmp[0]));
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`BASE`MODULE `SHIFT_UNIT_MULT mult_byte1 ( .a({sign[1], din[23:16] ,din[15:8], din[7:0]}), .b({1'b0,s1}), .p(tmp[1]));
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`BASE`MODULE `SHIFT_UNIT_MULT mult_byte0 ( .a({sign[0], din[15:8] ,din[7:0], 8'h00}), .b({1'b0,s1}), .p(tmp[0]));
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`undef MODULE
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// second stage is multiplexer based
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// second stage is multiplexer based
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// shift on byte level
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// shift on byte level
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// mux byte 3
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// mux byte 3
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assign dout[31:24] = (s[4:3]==2'b00) ? tmp[3] :
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assign dout[31:24] = (s[4:3]==2'b00) ? tmp[3] :
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(s[4:3]==2'b01) ? tmp[1] :
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(s[4:3]==2'b01) ? tmp[1] :
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(s[4:3]==2'b10) ? tmp[2] :
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(s[4:3]==2'b10) ? tmp[2] :
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tmp[3];
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tmp[3];
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endmodule
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endmodule
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`endif
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`ifdef LOGIC_UNIT
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// logic unit
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// logic unit
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// supporting the following logic functions
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// supporting the following logic functions
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// a and b
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// a and b
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// a or b
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// a or b
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// a xor b
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// a xor b
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// not b
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// not b
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module vl_logic_unit( a, b, result, opcode);
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`define MODULE logic_unit
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module `BASE`MODULE( a, b, result, opcode);
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`undef MODULE
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parameter width = 32;
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parameter width = 32;
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parameter opcode_and = 2'b00;
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parameter opcode_and = 2'b00;
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parameter opcode_or = 2'b01;
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parameter opcode_or = 2'b01;
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parameter opcode_xor = 2'b10;
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parameter opcode_xor = 2'b10;
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input [width-1:0] a,b;
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input [width-1:0] a,b;
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assign {c_out,result} = {(a[width-1] & sign),a} + ({a[width-1] & sign,b} ^ {(width+1){(add_sub==opcode_sub)}}) + {{(width-1){1'b0}},(c_in | (add_sub==opcode_sub))};
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assign {c_out,result} = {(a[width-1] & sign),a} + ({a[width-1] & sign,b} ^ {(width+1){(add_sub==opcode_sub)}}) + {{(width-1){1'b0}},(c_in | (add_sub==opcode_sub))};
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assign z = (result=={width{1'b0}});
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assign z = (result=={width{1'b0}});
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assign ovfl = ( a[width-1] & b[width-1] & ~result[width-1]) |
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assign ovfl = ( a[width-1] & b[width-1] & ~result[width-1]) |
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(~a[width-1] & ~b[width-1] & result[width-1]);
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(~a[width-1] & ~b[width-1] & result[width-1]);
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endmodule
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endmodule
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`endif
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